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Subversion Repositories klc32

[/] [klc32/] [trunk/] [rtl/] [verilog/] [WRITEBACK.v] - Diff between revs 2 and 10

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Rev 2	Rev 10
Line 21...	Line 21...
`//`	`//`
`// ============================================================================`	`// ============================================================================`
`//`	`//`
`WRITEBACK:`	`WRITEBACK:`
`begin`	`begin`
if (opcode==`POP)
`state <= POP1;`
`else`
`state <= WRITE_FLAGS;`	`state <= WRITE_FLAGS;`
if (opcode!=`CMPI && !(opcode==`RR && func==`CMP)) begin	if (opcode!=`CMPI && !(opcode==`RR && func==`CMP)) begin
`regfile[Rn] <= res;`	`regfile[Rn] <= res;`
`if (Rn==5'd31) begin`	`if (Rn==5'd31) begin`
`if (sf) ssp <= res;`	`if (sf) ssp <= res;`
Line 37...	Line 34...
`case(opcode)`	`case(opcode)`
`R:	`R:
`case(func)`	`case(func)`
`ABS:	`ABS:
`begin`	`begin`
	`if (!Rcbit) state <= IFETCH;`
`vf <= res[31];`	`vf <= res[31];`
`cf <= 1'b0;`	`cf <= 1'b0;`
`nf <= res[31];`	`nf <= res[31];`
`zf <= res==32'd0;`	`zf <= res==32'd0;`
`end`	`end`
`SGN,`NOT,`EXTB,`EXTH:	`SGN,`NOT,`EXTB,`EXTH:
`begin`	`begin`
	`if (!Rcbit) state <= IFETCH;`
`vf <= 1'b0;`	`vf <= 1'b0;`
`cf <= 1'b0;`	`cf <= 1'b0;`
`nf <= res[31];`	`nf <= res[31];`
`zf <= res==32'd0;`	`zf <= res==32'd0;`
`end`	`end`
`NEG:	`NEG:
`begin`	`begin`
	`if (!Rcbit) state <= IFETCH;`
`vf <= v_rr;`	`vf <= v_rr;`
`cf <= c_rr;`	`cf <= c_rr;`
`nf <= res[31];`	`nf <= res[31];`
`zf <= res==32'd0;`	`zf <= res==32'd0;`
`end`	`end`
`endcase`	`endcase`
`RR:	`RR:
`case(func)`	`case(func)`
`ADD,`SUB:	`ADD,`SUB:
`begin`	`begin`
	`if (!Rcbit) state <= IFETCH;`
`vf <= v_rr;`	`vf <= v_rr;`
`cf <= c_rr;`	`cf <= c_rr;`
`nf <= res[31];`	`nf <= res[31];`
`zf <= res==32'd0;`	`zf <= res==32'd0;`
`end`	`end`
`CMP:	`CMP:
`begin`	`begin`
	`state <= WRITE_FLAGS;`
`vf <= 1'b0;`	`vf <= 1'b0;`
`cf <= c_rr;`	`cf <= c_rr;`
`nf <= res[31];`	`nf <= res[31];`
`zf <= res==32'd0;`	`zf <= res==32'd0;`
`end`	`end`
`AND,`OR,`EOR,`NAND,`NOR,`ENOR,`MIN,`MAX,	`AND,`OR,`EOR,`NAND,`NOR,`ENOR,`MIN,`MAX,
`LWX,`LHX,`LBX,`LHUX,`LBUX:	`LWX,`LHX,`LBX,`LHUX,`LBUX:
`begin`	`begin`
	`if (!Rcbit) state <= IFETCH;`
`vf <= 1'b0;`	`vf <= 1'b0;`
`cf <= 1'b0;`	`cf <= 1'b0;`
`nf <= res[31];`	`nf <= res[31];`
`zf <= res==32'd0;`	`zf <= res==32'd0;`
`end`	`end`
`SHL,`ROL:	`SHL,`ROL:
`begin`	`begin`
	`if (!Rcbit) state <= IFETCH;`
`vf <= 1'b0;`	`vf <= 1'b0;`
`cf <= shlo[32];`	`cf <= shlo[32];`
`nf <= res[31];`	`nf <= res[31];`
`zf <= res==32'd0;`	`zf <= res==32'd0;`
`end`	`end`
`SHR,`ROR:	`SHR,`ROR:
`begin`	`begin`
	`if (!Rcbit) state <= IFETCH;`
`vf <= 1'b0;`	`vf <= 1'b0;`
`cf <= shro[31];`	`cf <= shro[31];`
`nf <= res[31];`	`nf <= res[31];`
`zf <= res==32'd0;`	`zf <= res==32'd0;`
`end`	`end`
`BCDADD:	`BCDADD:
`begin`	`begin`
	`if (!Rcbit) state <= IFETCH;`
`vf <= 1'b0;`	`vf <= 1'b0;`
`cf <= bcdaddc;`	`cf <= bcdaddc;`
`nf <= res[7];`	`nf <= res[7];`
`zf <= res[7:0]==8'd0;`	`zf <= res[7:0]==8'd0;`
`end`	`end`
`BCDSUB:	`BCDSUB:
`begin`	`begin`
	`if (!Rcbit) state <= IFETCH;`
`vf <= 1'b0;`	`vf <= 1'b0;`
`cf <= bcdsubc;`	`cf <= bcdsubc;`
`nf <= res[7];`	`nf <= res[7];`
`zf <= res[7:0]==8'd0;`	`zf <= res[7:0]==8'd0;`
`end`	`end`
	`DIVU,`DIVS,`MODU,`MODS:
	`begin`
	`if (!Rcbit) state <= IFETCH;`
	`vf <= divByZero;`
	`cf <= divByZero;`
	`nf <= res[31];`
	`zf <= res==32'd0;`
	`end`
	`MULU,`MULS,`MULUH,`MULSH:
	`begin`
	`if (!Rcbit) state <= IFETCH;`
	`cf <= vf;`
	`nf <= res[31];`
	`zf <= res==32'd0;`
	`end`
`endcase`	`endcase`
`ADDI,`SUBI:	`ADDI,`SUBI:
`begin`	`begin`
`vf <= v_ri;`	`vf <= v_ri;`
`cf <= c_ri;`	`cf <= c_ri;`
Line 131...	Line 153...
`vf <= 1'b0;`	`vf <= 1'b0;`
`cf <= 1'b0;`	`cf <= 1'b0;`
`nf <= res[31];`	`nf <= res[31];`
`zf <= res==32'd0;`	`zf <= res==32'd0;`
`end`	`end`
	`DIVSI,`DIVUI:
	`begin`
	`vf <= divByZero;`
	`cf <= divByZero;`
	`nf <= res[31];`
	`zf <= res==32'd0;`
	`end`
	`MULSI,`MULUI:
	`begin`
	`cf <= vf;`
	`nf <= res[31];`
	`zf <= res==32'd0;`
	`end`
	`POP: state <= POP1;
`LINK:	`LINK:
`begin`	`begin`
`state <= IFETCH;`	`state <= IFETCH;`
`if (sf)`	`if (sf)`
`ssp <= ssp + imm;`	`ssp <= ssp - imm;`
`else`	`else`
`usp <= usp + imm;`	`usp <= usp - imm;`
`end`	`end`
`endcase`	`endcase`
`end`	`end`


`No newline at end of file`	`No newline at end of file`

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Subversion Repositories klc32

[/] [klc32/] [trunk/] [rtl/] [verilog/] [WRITEBACK.v] - Diff between revs 2 and 10