| Line 23... |
Line 23... |
//
|
//
|
WRITE_FLAGS:
|
WRITE_FLAGS:
|
begin
|
begin
|
state <= IFETCH;
|
state <= IFETCH;
|
if (opcode==`CMPI || (opcode==`RR && func==`CMP)) begin
|
if (opcode==`CMPI || (opcode==`RR && func==`CMP)) begin
|
case(Rn[2:0])
|
case(Rn[4:2])
|
3'd0: cr0 <= {nf,zf,vf,cf};
|
3'd0: cr0 <= {nf,zf,vf,cf};
|
3'd1: cr1 <= {nf,zf,vf,cf};
|
3'd1: cr1 <= {nf,zf,vf,cf};
|
3'd2: cr2 <= {nf,zf,vf,cf};
|
3'd2: cr2 <= {nf,zf,vf,cf};
|
3'd3: cr3 <= {nf,zf,vf,cf};
|
3'd3: cr3 <= {nf,zf,vf,cf};
|
3'd4: cr4 <= {nf,zf,vf,cf};
|
3'd4: cr4 <= {nf,zf,vf,cf};
|
| Line 39... |
Line 39... |
else begin
|
else begin
|
case(opcode)
|
case(opcode)
|
`R:
|
`R:
|
case(func)
|
case(func)
|
`ABS,`SGN,`NEG,`NOT,`EXTB,`EXTH:
|
`ABS,`SGN,`NEG,`NOT,`EXTB,`EXTH:
|
cr0 <= {nf,zf,vf,cf};
|
if (Rcbit) cr0 <= {nf,zf,vf,cf};
|
default: ;
|
default: ;
|
endcase
|
endcase
|
`RR:
|
`RR:
|
case(func)
|
case(func)
|
`ADD,`SUB,`AND,`OR,`EOR,`NAND,`NOR,`ENOR,
|
`MULU,`MULS,`MULUH,`MULSH,`DIVU,`DIVS,`MODU,`MODS,
|
|
`ADD,`SUB,`AND,`ANDC,`OR,`ORC,`EOR,`NAND,`NOR,`ENOR,
|
`MIN,`MAX,
|
`MIN,`MAX,
|
`BCDADD,`BCDSUB,
|
`BCDADD,`BCDSUB,
|
`SHL,`SHR,`ROL,`ROR,
|
`SHL,`SHR,`ROL,`ROR,
|
`LWX,`LHX,`LBX,`LHUX,`LBUX:
|
`LWX,`LHX,`LBX,`LHUX,`LBUX:
|
cr0 <= {nf,zf,vf,cf};
|
if (Rcbit) cr0 <= {nf,zf,vf,cf};
|
default: ;
|
default: ;
|
endcase
|
endcase
|
|
`MULUI,`MULSI,`DIVUI,`DIVSI,
|
`ADDI,`SUBI,`ANDI,`ORI,`EORI,`LW,`LH,`LB,`LHU,`LBU,`TAS:
|
`ADDI,`SUBI,`ANDI,`ORI,`EORI,`LW,`LH,`LB,`LHU,`LBU,`TAS:
|
cr0 <= {nf,zf,vf,cf};
|
cr0 <= {nf,zf,vf,cf};
|
default: ;
|
default: ;
|
endcase
|
endcase
|
end
|
end
|
