OpenCores
URL https://opencores.org/ocsvn/layer2/layer2/trunk

Subversion Repositories layer2

[/] [layer2/] [trunk/] [sw/] [common/] [boot.s] - Diff between revs 2 and 6

Show entire file | Details | Blame | View Log

Rev 2 Rev 6
Line 97... Line 97...
        .set    reorder
        .set    reorder
        .end    boot
        .end    boot
 
 
 
 
################################################################################
################################################################################
# Interrupt Start                                                              #
 
#------------------------------------------------------------------------------#
 
        # .ent  intr_handler
 
# intr_handler:
 
        # .set  noreorder
 
        # .set  noat
 
 
 
# If we do not include the Interrupt API, simply return to normal execution
 
# immediately.
 
# .ifdef _INTERRUPT
 
 
 
        # addiu $sp, $sp, -72            # Allocate space for all relevant registers.
 
        # sw       $at,  4($sp)            # Save all registers, that are used directily
 
        # sw       $v0,  8($sp)            # after a successful execution of the interrupt
 
        # sw       $v1, 12($sp)            # service routines.
 
        # sw       $a0, 16($sp)            # Registers $s0 - $s8 do not need to be saved,
 
        # sw       $a1, 20($sp)            # since the compiler stores them if they are
 
        # sw       $a2, 24($sp)            # used in a procedure.
 
        # sw       $a3, 28($sp)            # $gp is the same for the entire source code.
 
        # sw       $t0, 32($sp)            # Registers $k0 and $k1 are reserved for ASM
 
        # sw       $t1, 36($sp)            # routines. The C compiler does not use them.
 
        # sw       $t2, 40($sp)
 
        # sw       $t3, 44($sp)
 
        # sw       $t4, 48($sp)
 
        # sw       $t5, 52($sp)
 
        # sw       $t6, 56($sp)
 
        # sw       $t7, 60($sp)
 
        # sw       $t8, 64($sp)
 
        # sw       $t9, 68($sp)
 
        # sw       $ra, 72($sp)
 
 
 
        # mfc0  $k0, $13                            # Retrieve CAUSE (Pending Interrupts).
 
        #nop
 
        # mfc0  $k1, $12                            # Retrieve SR (Interrupt mask and global IE).
 
        # nop
 
        # and   $k0, $k0, $k1            # Get legal pending interrupts.
 
        # addiu $sp, $sp, -24
 
        # jal   intr_dispatch           # Jump to C interrupt dispatch routine.
 
   # srl        $a0, $k0, 8
 
   # addiu $sp, $sp, 24
 
 
 
        # lw       $at,  4($sp)            # Restore saved registers.
 
        # lw       $v0,  8($sp)
 
        # lw       $v1, 12($sp)
 
        # lw       $a0, 16($sp)
 
        # lw       $a1, 20($sp)
 
        # lw       $a2, 24($sp)
 
        # lw       $a3, 28($sp)
 
        # lw       $t0, 32($sp)
 
        # lw       $t1, 36($sp)
 
        # lw       $t2, 40($sp)
 
        # lw       $t3, 44($sp)
 
        # lw       $t4, 48($sp)
 
        # lw       $t5, 52($sp)
 
        # lw       $t6, 56($sp)
 
        # lw       $t7, 60($sp)
 
        # lw       $t8, 64($sp)
 
        # lw       $t9, 68($sp)
 
        # lw       $ra, 72($sp)
 
        # addiu $sp, $sp, 72          # Undo stack allocation.
 
 
 
# .endif
 
 
 
        # mfc0  $k1, $14                            # Retrieve EPC
 
        # nop
 
        # jr       $k1                     # Return to normal execution.
 
        # rfe                                     # Restore from exception. Pop IE stack.
 
 
 
   # .set  at
 
        # .set  reorder
 
        # .end  intr_handler
 
 
 
 
 
################################################################################
 
# Start Flash Application                                                      #
# Start Flash Application                                                      #
#------------------------------------------------------------------------------#
#------------------------------------------------------------------------------#
   .globl   start
   .globl   start
        .ent       start
        .ent       start
start:
start:

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.