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https://opencores.org/ocsvn/layer2/layer2/trunk
[/] [layer2/] [trunk/] [vhdl/] [ddr/] [rtl/] [ddr.vhd] - Diff between revs 2 and 4
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| Rev 2 |
Rev 4 |
| Line 170... |
Line 170... |
-- communication protocol implementation, which does not allow a master
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-- communication protocol implementation, which does not allow a master
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-- and a slave running at different frequencies.
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-- and a slave running at different frequencies.
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-- If this problem happens to be fixed someday, the following state
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-- If this problem happens to be fixed someday, the following state
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-- machine can be deleted and the Wishbone signals can be tied directly
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-- machine can be deleted and the Wishbone signals can be tied directly
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-- into the main state machine.
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-- into the main state machine.
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wbone : process(w, si, init.done)
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wbone : process(w, si, init.done, ddr_done)
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begin
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begin
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win <= w;
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win <= w;
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so.ack <= '0';
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so.ack <= '0';
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| Line 215... |
Line 215... |
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Main Controller --
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-- Main Controller --
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- main : process(m, si, init)
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-- main : process(m, si, init)
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main : process(m, init, read_wb, write_wb)
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main : process(m, init, read_wb, write_wb, si.adr)
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begin
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begin
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min <= m;
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min <= m;
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-- Refresh counter.
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-- Refresh counter.
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