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##############################################################
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##############################################################
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#
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#
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# Xilinx Core Generator version 13.4
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# Xilinx Core Generator version 13.4
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# Date: Tue May 22 23:21:52 2012
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# Date: Thu May 24 16:40:57 2012
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#
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#
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##############################################################
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##############################################################
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#
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#
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# This file contains the customisation parameters for a
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# This file contains the customisation parameters for a
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# Xilinx CORE Generator IP GUI. It is strongly recommended
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# Xilinx CORE Generator IP GUI. It is strongly recommended
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# BEGIN Select
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# BEGIN Select
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SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.05.a
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SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.05.a
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# END Select
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# END Select
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# BEGIN Parameters
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# BEGIN Parameters
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CSET asynchronous_input_port_width=8
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CSET asynchronous_input_port_width=8
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CSET asynchronous_output_port_width=19
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CSET asynchronous_output_port_width=8
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CSET component_name=coreVIO
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CSET component_name=coreVIO
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CSET constraint_type=external
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CSET constraint_type=external
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CSET enable_asynchronous_input_port=false
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CSET enable_asynchronous_input_port=false
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CSET enable_asynchronous_output_port=true
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CSET enable_asynchronous_output_port=false
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CSET enable_synchronous_input_port=false
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CSET enable_synchronous_input_port=false
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CSET enable_synchronous_output_port=false
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CSET enable_synchronous_output_port=true
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CSET example_design=true
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CSET example_design=true
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CSET invert_clock_input=false
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CSET invert_clock_input=true
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CSET synchronous_input_port_width=8
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CSET synchronous_input_port_width=8
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CSET synchronous_output_port_width=8
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CSET synchronous_output_port_width=19
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# END Parameters
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# END Parameters
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# BEGIN Extra information
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# BEGIN Extra information
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MISC pkg_timestamp=2012-01-07T09:20:13Z
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MISC pkg_timestamp=2012-01-07T09:20:13Z
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# END Extra information
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# END Extra information
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GENERATE
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GENERATE
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# CRC: 8c8e6067
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# CRC: d7309c64
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# CRC: d7309c64
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# CRC: d7309c64
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