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[/] [lcd_block/] [trunk/] [hdl/] [iseProject/] [lcd_wishbone_slave.v] - Diff between revs 3 and 5
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/*
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/*
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Wishbone slave
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Wishbone slave
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(Verilog 2001)
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(Verilog 2001)
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*/
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*/
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module lcd_wishbone_slave(
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module lcd_wishbone_slave(
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input RST_I,
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input clk_i,
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input CLK_I,
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input rst_i,
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input [1:0] ADR_I0,
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input [1:0] wb_adr_i,
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input DAT_I0,
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input [7:0] wb_dat_i,
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output [7:0] DAT_O0,
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output [7:0] wb_dat_o,
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input WE_I,
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input wb_we_i,
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input SEL_I0,
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input SEL_I0,
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input STB_I,
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input wb_stb_i,
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output ACK_O,
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output wb_ack_o,
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input CYC_I
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input CYC_I
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);
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);
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endmodule
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endmodule
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