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[/] [lcd_block/] [trunk/] [hdl/] [iseProject/] [testLcd_controller.v] - Diff between revs 8 and 10
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Rev 10 |
| Line 42... |
Line 42... |
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initial
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initial
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begin
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begin
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// Initialize Inputs
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// Initialize Inputs
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$display($time, " << Starting the Simulation >>");
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$display($time, " << Starting the Simulation >>");
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$monitor ("lcd_e=%b,lcd_nibble=%b,done=%b", lcd_e,lcd_nibble,done);
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rst = 1;
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rst = 1;
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clk = 0;
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clk = 0;
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rs_in = 0;
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data_in = 0;
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data_in = 0;
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strobe_in = 0;
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strobe_in = 0;
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period_clk_ns = 20; // Indicate the number of time at each cycle (20 ns in our case)
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period_clk_ns = 20; // Indicate the number of time at each cycle (20 ns in our case)
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// Wait for one clock cycle to reset
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// Wait for one clock cycle to reset
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Line 60... |
// Like wait until... from Verilog
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// Like wait until... from Verilog
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@(posedge uut.lcd_init_done);
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@(posedge uut.lcd_init_done);
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data_in = 65;
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data_in = 65;
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#20 strobe_in = 1; #20 strobe_in = 0;
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#20 strobe_in = 1; #20 strobe_in = 0;
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@(posedge done);
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@(posedge done);
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// Finish simulation (on VHDL assert false report...)
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$finish;
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end
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end
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endmodule
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endmodule
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