URL https://opencores.org/ocsvn/lcd_block/lcd_block/trunk

Subversion Repositories lcd_block

[/] [lcd_block/] [trunk/] [hdl/] [iseProject/] [testLcd_controller.v] - Diff between revs 6 and 8

Rev 6	Rev 8
Line 3...	Line 3...
`module testLcd_controller;`	`module testLcd_controller;`

`// Inputs`	`// Inputs`
`reg rst;`	`reg rst;`
`reg clk;`	`reg clk;`
	`reg rs_in;`
`reg [7:0] data_in;`	`reg [7:0] data_in;`
`reg strobe_in;`	`reg strobe_in;`
`reg [7:0] period_clk_ns;`	`reg [7:0] period_clk_ns;`

`// Outputs`	`// Outputs`
Line 19...	Line 20...

`// Instantiate the Unit Under Test (UUT)`	`// Instantiate the Unit Under Test (UUT)`
`lcd_controller uut (`	`lcd_controller uut (`
`.rst(rst),`	`.rst(rst),`
`.clk(clk),`	`.clk(clk),`
	`.rs_in(rs_in),`
`.data_in(data_in),`	`.data_in(data_in),`
`.strobe_in(strobe_in),`	`.strobe_in(strobe_in),`
`.period_clk_ns(period_clk_ns),`	`.period_clk_ns(period_clk_ns),`
`.lcd_e(lcd_e),`	`.lcd_e(lcd_e),`
`.lcd_nibble(lcd_nibble),`	`.lcd_nibble(lcd_nibble),`
Line 50...	Line 52...

`// Wait for one clock cycle to reset`	`// Wait for one clock cycle to reset`
`#20;`	`#20;`
`rst = 0;`	`rst = 0;`

`// Add stimulus here`	`// One advantege over of Verilog over VHDL (Access to internal signals...)`
	`// Like wait until... from Verilog`
	`@(posedge uut.lcd_init_done);`
	`data_in = 65;`
	`#20 strobe_in = 1; #20 strobe_in = 0;`
	`@(posedge done);`
`end`	`end`

`endmodule`	`endmodule`


`No newline at end of file`	`No newline at end of file`