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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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/*
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/*
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Top module that will instantiate and connect our DUT (lcd_controller) the ICON, VIO , ILA cores
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Top module that will instantiate and connect our DUT (lcd_controller) the ICON, VIO , ILA cores
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*/
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*/
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module top_hw_testbench(
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module top_hw_testbench(
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input clk/*,
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input clk,
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output hw_lcd_e,
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output hw_lcd_e,
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output hw_lcd_rs,
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output hw_lcd_rs,
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output hw_lcd_rw,
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output hw_lcd_rw,
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output [3:0] hw_lcd_nibble,
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output [3:0] hw_lcd_nibble,
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output hw_strata_flash_disable*/
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output hw_strata_flash_disable
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);
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);
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// Declare some wires to connect the components
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// Declare some wires to connect the components
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wire rst;
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wire rst;
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wire rs_in,strobe_in;
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wire rs_in,strobe_in;
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assign trig_0 = lcd_e;
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assign trig_0 = lcd_e;
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assign {rst, rs_in, data_in, strobe_in, period_clk_ns} = async_out;
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assign {rst, rs_in, data_in, strobe_in, period_clk_ns} = async_out;
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assign data = {7'd1,lcd_e, lcd_nibble[3:0], lcd_rs, lcd_rw, disable_flash, done, strobe_in};
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assign data = {7'd1,lcd_e, lcd_nibble[3:0], lcd_rs, lcd_rw, disable_flash, done, strobe_in};
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// Send all interest output to outside
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// Send all interest output to outside
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/*assign hw_lcd_e = lcd_e;
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assign hw_lcd_e = lcd_e;
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assign hw_lcd_rs = lcd_rs;
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assign hw_lcd_rs = lcd_rs;
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assign hw_lcd_rw = lcd_rw;
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assign hw_lcd_rw = lcd_rw;
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assign hw_lcd_nibble = lcd_nibble;
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assign hw_lcd_nibble = lcd_nibble;
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assign hw_strata_flash_disable = disable_flash;*/
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assign hw_strata_flash_disable = disable_flash;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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