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https://opencores.org/ocsvn/lfsr_randgen/lfsr_randgen/trunk
[/] [lfsr_randgen/] [trunk/] [lfsr_tb.vhd] - Diff between revs 2 and 4
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entity lfsr_tb is
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entity lfsr_tb is
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end lfsr_tb;
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end lfsr_tb;
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architecture behavior of lfsr_tb is
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architecture behavior of lfsr_tb is
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signal width : integer :=8; --change the width value here for a different regsiter width.
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constant width : integer :=8; --change the width value here for a different regsiter width.
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signal clk,set_seed,out_enable : std_logic := '0';
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signal clk,set_seed : std_logic := '0';
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signal seed : std_logic_vector(width-1 downto 0) := (0 => '1',others => '0');
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signal seed : std_logic_vector(width-1 downto 0) := (0 => '1',others => '0');
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signal rand_out : std_logic_vector(width-1 downto 0);
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signal rand_out : std_logic_vector(width-1 downto 0);
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-- clock period definitions
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-- clock period definitions
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constant clk_period : time := 1 ns;
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constant clk_period : time := 1 ns;
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begin
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begin
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-- entity instantiation for the lfsr component.
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-- entity instantiation for the lfsr component.
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uut: entity work.lfsr generic map (width => 8) --change the width value here for a different regsiter width.
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uut: entity work.lfsr generic map (width => width) --change the width value here for a different regsiter width.
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PORT MAP (
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PORT MAP (
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clk => clk,
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clk => clk,
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set_seed => set_seed,
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set_seed => set_seed,
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out_enable => out_enable,
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seed => seed,
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seed => seed,
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rand_out => rand_out
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rand_out => rand_out
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);
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);
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-- Clock process definitions
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-- Clock process definitions
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wait for 10 ns;
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wait for 10 ns;
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set_seed <= '1';
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set_seed <= '1';
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wait for 1 ns;
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wait for 1 ns;
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set_seed <= '0';
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set_seed <= '0';
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wait for 20 ns;
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wait for 20 ns;
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out_enable <= '1';
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wait;
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wait;
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end process;
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end process;
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END;
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END;
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