| Line 12... |
Line 12... |
//
|
//
|
// Operation 1 sets up the ALU input registers; operation 2 takes the ALU result
|
// Operation 1 sets up the ALU input registers; operation 2 takes the ALU result
|
// and writes it back somewhere; and the flags group all other microinstruction
|
// and writes it back somewhere; and the flags group all other microinstruction
|
// control signals.
|
// control signals.
|
//
|
//
|
// For any given instruction, operation 2 takes place in the cycle following
|
// For any given microinstruction, operation 2 takes place in the cycle after
|
// operation 1. It happens concurrently with the next instruction's operation 1,
|
// operation 1. It happens concurrently with the next microinstruction's
|
// so whenever a register is written to in an operation 2 it will NOT be
|
// operation 1, so whenever a register is written to in an operation 2 it will
|
// available for the next instruction.
|
// NOT be available for the next microinstruction.
|
//
|
//
|
// In operation 1, you may load any one of T1 or T2 from the register bank or
|
// In operation 1, you may load any one of T1 or T2 from the register bank or
|
// from DI which is simply the unregistered signal data_in.
|
// from DI which is simply the unregistered signal data_in.
|
//
|
//
|
// In operation 2, you specify the ALU operation and assign the ALU result to
|
// In operation 2, you specify the ALU operation and assign the ALU result to
|
| Line 49... |
Line 49... |
// #setacy : Set aux carry at the start of 1st cycle (used for ++).
|
// #setacy : Set aux carry at the start of 1st cycle (used for ++).
|
// #end : Jump to microinstruction address 3 after the present m.i.
|
// #end : Jump to microinstruction address 3 after the present m.i.
|
// #ret : Jump to address saved by the last JST or TJSR m.i.
|
// #ret : Jump to address saved by the last JST or TJSR m.i.
|
// #rd : Activate rd signal for the 2nd cycle.
|
// #rd : Activate rd signal for the 2nd cycle.
|
// #wr : Activate wr signal for the 2nd cycle.
|
// #wr : Activate wr signal for the 2nd cycle.
|
// #fp_r : This instruction updates all PSW flags except for C.
|
// #fp_r : This microinstruction updates all PSW flags except for C.
|
// #fp_c : This instruction updates only the C flag in the PSW.
|
// #fp_c : This microinstruction updates only the C flag in the PSW.
|
// #fp_rc : This instruction updates all the flags in the PSW.
|
// #fp_rc : This microinstruction updates all the flags in the PSW.
|
// #clrt1 : Clear T1 at the end of 1st cycle.
|
// #clrt1 : Clear T1 at the end of 1st cycle.
|
// #io : Activate io signal for 1st cycle.
|
// #io : Activate io signal for 1st cycle.
|
// #ei : Set interrupt enable register.
|
// #ei : Set interrupt enable register.
|
// #di : Reset interrupt enable register.
|
// #di : Reset interrupt enable register.
|
// #halt : Jump to microcode address 0x07 without saving return value.
|
// #halt : Jump to microcode address 0x07 without saving return value.
|
| Line 534... |
Line 534... |
JSR push
|
JSR push
|
T1 = _pl ; DO = T1 ; #clrt1
|
T1 = _pl ; DO = T1 ; #clrt1
|
JSR push
|
JSR push
|
NOP ; _pl = rst ; #clrt1
|
NOP ; _pl = rst ; #clrt1
|
NOP ; _ph = AND ; #end // T1 & T2 = 0, because T2=0
|
NOP ; _ph = AND ; #end // T1 & T2 = 0, because T2=0
|
// No extra cycle needed, _ph is not used in the next instruction
|
// No extra cycle needed, _ph is not used in the next microinstruction
|
|
|
__code "11101001"
|
__code "11101001"
|
__asm PCHL
|
__asm PCHL
|
|
|
T1 = _l ; NOP
|
T1 = _l ; NOP
|
