| Line 33... |
Line 33... |
//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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// test bench global defines
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// test bench global defines
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// the following define selects between CPU instruction trace and uart transmitted bytes
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// the following define selects between CPU instruction trace and uart transmitted bytes
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//`define CPU_TRACE 1
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//`define CPU_TRACE 1
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//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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// internal signals
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// internal signals
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reg clock; // global clock
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reg clock; // global clock
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reg reset; // global reset
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reg reset; // global reset
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// UUT interfaces
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// UUT interfaces
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wire rxd, txd;
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wire rxd, txd;
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wire [7:0] p1dio, p2dio;
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wire [7:0] p1dio, p2dio;
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wire [3:0] extint;
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reg sp1dio0;
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//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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// test bench implementation
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// test bench implementation
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// global signals generation
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// global signals generation
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initial
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initial
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| Line 91... |
Line 92... |
.clock(clock),
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.clock(clock),
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.reset(reset),
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.reset(reset),
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.txd(txd),
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.txd(txd),
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.rxd(rxd),
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.rxd(rxd),
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.p1dio(p1dio),
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.p1dio(p1dio),
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.p2dio(p2dio)
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.p2dio(p2dio),
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.extint(extint)
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);
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);
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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// uart receive is not used in this test becnch
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// uart receive is not used in this test becnch
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assign rxd = 1'b1;
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assign rxd = 1'b1;
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// external interrupt 0 is connected to the p1dio[0] rising edge
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assign extint[3:1] = 3'b0;
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assign extint[0] = ((sp1dio0 == 1'b0) && (p1dio[0] == 1'b1)) ? 1'b1 : 1'b0;
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// p1dio[0] rising edge detection
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always @ (posedge reset or posedge clock)
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begin
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if (reset)
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sp1dio0 <= 1'b0;
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else if (p1dio[0] == 1'b1)
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sp1dio0 <= 1'b1;
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else
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sp1dio0 <= 1'b0;
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end
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//------------------------------------------------------------------
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// test bench output log selection - either simple CPU trace or UART
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// transmit port log
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`ifdef CPU_TRACE
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`ifdef CPU_TRACE
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// display executed instructions
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// display executed instructions
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reg [15:0] saddr;
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reg [15:0] saddr;
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reg scpu_rd;
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reg scpu_rd;
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always @ (posedge clock)
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always @ (posedge clock)
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