OpenCores
URL https://opencores.org/ocsvn/light8080/light8080/trunk

Subversion Repositories light8080

[/] [light8080/] [trunk/] [verilog/] [bench/] [tb_l80soc.v] - Diff between revs 65 and 66

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 65 Rev 66
Line 33... Line 33...
//---------------------------------------------------------------------------------------
//---------------------------------------------------------------------------------------
// test bench global defines 
// test bench global defines 
// the following define selects between CPU instruction trace and uart transmitted bytes 
// the following define selects between CPU instruction trace and uart transmitted bytes 
//`define CPU_TRACE             1
//`define CPU_TRACE             1
 
 
 
 
//---------------------------------------------------------------------------------------
//---------------------------------------------------------------------------------------
// internal signals 
// internal signals 
reg clock;                              // global clock 
reg clock;                              // global clock 
reg reset;                              // global reset 
reg reset;                              // global reset 
 
 
// UUT interfaces 
// UUT interfaces 
wire rxd, txd;
wire rxd, txd;
wire [7:0] p1dio, p2dio;
wire [7:0] p1dio, p2dio;
 
wire [3:0] extint;
 
reg sp1dio0;
 
 
//---------------------------------------------------------------------------------------
//---------------------------------------------------------------------------------------
// test bench implementation 
// test bench implementation 
// global signals generation  
// global signals generation  
initial
initial
Line 91... Line 92...
        .clock(clock),
        .clock(clock),
        .reset(reset),
        .reset(reset),
        .txd(txd),
        .txd(txd),
        .rxd(rxd),
        .rxd(rxd),
        .p1dio(p1dio),
        .p1dio(p1dio),
        .p2dio(p2dio)
        .p2dio(p2dio),
 
        .extint(extint)
);
);
 
 
//------------------------------------------------------------------
//------------------------------------------------------------------
// uart receive is not used in this test becnch 
// uart receive is not used in this test becnch 
assign rxd = 1'b1;
assign rxd = 1'b1;
 
 
 
// external interrupt 0 is connected to the p1dio[0] rising edge 
 
assign extint[3:1] = 3'b0;
 
assign extint[0] = ((sp1dio0 == 1'b0) && (p1dio[0] == 1'b1)) ? 1'b1 : 1'b0;
 
 
 
// p1dio[0] rising edge detection 
 
always @ (posedge reset or posedge clock)
 
begin
 
        if (reset)
 
                sp1dio0 <= 1'b0;
 
        else if (p1dio[0] == 1'b1)
 
                sp1dio0 <= 1'b1;
 
        else
 
                sp1dio0 <= 1'b0;
 
end
 
 
 
//------------------------------------------------------------------
 
// test bench output log selection - either simple CPU trace or UART 
 
// transmit port log 
`ifdef CPU_TRACE
`ifdef CPU_TRACE
// display executed instructions 
// display executed instructions 
reg [15:0] saddr;
reg [15:0] saddr;
reg scpu_rd;
reg scpu_rd;
always @ (posedge clock)
always @ (posedge clock)

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.