OpenCores
URL https://opencores.org/ocsvn/light8080/light8080/trunk

Subversion Repositories light8080

[/] [light8080/] [trunk/] [verilog/] [rtl/] [l80soc.v] - Diff between revs 65 and 66

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 65 Rev 66
Line 30... Line 30...
 
 
module l80soc
module l80soc
(
(
        clock, reset,
        clock, reset,
        txd, rxd,
        txd, rxd,
        p1dio, p2dio
        p1dio, p2dio,
 
        extint
);
);
//---------------------------------------------------------------------------------------
//---------------------------------------------------------------------------------------
// module interfaces 
// module interfaces 
// global signals 
// global signals 
input                   clock;          // global clock input 
input                   clock;          // global clock input 
Line 43... Line 44...
output                  txd;            // serial data output 
output                  txd;            // serial data output 
input                   rxd;            // serial data input 
input                   rxd;            // serial data input 
// digital IO ports 
// digital IO ports 
inout   [7:0]    p1dio;          // port 1 digital IO 
inout   [7:0]    p1dio;          // port 1 digital IO 
inout   [7:0]    p2dio;          // port 2 digital IO 
inout   [7:0]    p2dio;          // port 2 digital IO 
 
// external interrupt sources 
 
input   [3:0]    extint;         // external interrupt sources 
 
 
//---------------------------------------------------------------------------------------
//---------------------------------------------------------------------------------------
// io space registers addresses 
// io space registers addresses 
// uart registers 
// uart registers 
`define UDATA_REG                       8'h80           // used for both transmit and receive 
`define UDATA_REG                       8'h80           // used for both transmit and receive 
Line 56... Line 59...
// dio port registers 
// dio port registers 
`define P1_DATA_REG                     8'h84           // port 1 data register 
`define P1_DATA_REG                     8'h84           // port 1 data register 
`define P1_DIR_REG                      8'h85           // port 1 direction register 
`define P1_DIR_REG                      8'h85           // port 1 direction register 
`define P2_DATA_REG                     8'h86           // port 2 data register 
`define P2_DATA_REG                     8'h86           // port 2 data register 
`define P2_DIR_REG                      8'h87           // port 2 direction register 
`define P2_DIR_REG                      8'h87           // port 2 direction register 
 
// interrupt controller register 
 
`define INTR_EN_REG                     8'h88           // interrupts enable register 
 
 
//---------------------------------------------------------------------------------------
//---------------------------------------------------------------------------------------
// internal declarations 
// internal declarations 
// registered output 
// registered output 
 
 
// internals 
// internals 
wire [15:0] cpu_addr;
wire [15:0] cpu_addr;
wire [7:0] cpu_din, cpu_dout, ram_dout;
wire [7:0] cpu_din, cpu_dout, ram_dout, intr_dout;
wire cpu_io, cpu_rd, cpu_wr;
wire cpu_io, cpu_rd, cpu_wr, cpu_inta, cpu_inte, cpu_intr;
wire [7:0] txData;
wire [7:0] txData, rxData;
wire txValid, txBusy, rxValid, lcd_clk;
wire txValid, txBusy, rxValid;
wire [7:0] rxData;
 
reg [15:0] uartbaud;
reg [15:0] uartbaud;
reg rxfull, scpu_io;
reg rxfull, scpu_io;
reg [7:0] p1reg, p1dir, p2reg, p2dir, io_dout;
reg [7:0] p1reg, p1dir, p2reg, p2dir, io_dout;
 
reg [3:0] intr_ena;
 
 
//---------------------------------------------------------------------------------------
//---------------------------------------------------------------------------------------
// module implementation 
// module implementation 
// light8080 CPU instance 
// light8080 CPU instance 
light8080 cpu
light8080 cpu
Line 87... Line 92...
        .rd(cpu_rd),
        .rd(cpu_rd),
        .wr(cpu_wr),
        .wr(cpu_wr),
        .fetch(/* nu */),
        .fetch(/* nu */),
        .data_in(cpu_din),
        .data_in(cpu_din),
        .data_out(cpu_dout),
        .data_out(cpu_dout),
        .inta(/* nu */),
        .inta(cpu_inta),
        .inte(/* nu */),
        .inte(cpu_inte),
        .halt(/* nu */),
        .halt(/* nu */),
        .intr(1'b0)
        .intr(cpu_intr)
);
);
// cpu data input selection 
// cpu data input selection 
assign cpu_din = scpu_io ? io_dout : ram_dout;
assign cpu_din = (cpu_inta) ? intr_dout : (scpu_io) ? io_dout : ram_dout;
 
 
// program and data Xilinx RAM memory 
// program and data Xilinx RAM memory 
ram_image ram
ram_image ram
(
(
        .clk(clock),
        .clk(clock),
Line 116... Line 121...
                rxfull <= 1'b0;
                rxfull <= 1'b0;
                p1reg <= 8'b0;
                p1reg <= 8'b0;
                p1dir <= 8'b0;
                p1dir <= 8'b0;
                p2reg <= 8'b0;
                p2reg <= 8'b0;
                p2dir <= 8'b0;
                p2dir <= 8'b0;
 
                intr_ena <= 4'b0;
        end
        end
        else
        else
        begin
        begin
                // io space registers 
                // io space registers 
                if (cpu_wr && cpu_io)
                if (cpu_wr && cpu_io)
Line 128... Line 134...
                        if (cpu_addr[7:0] == `UBAUDH_REG)        uartbaud[15:8] <= cpu_dout;
                        if (cpu_addr[7:0] == `UBAUDH_REG)        uartbaud[15:8] <= cpu_dout;
                        if (cpu_addr[7:0] == `P1_DATA_REG)       p1reg <= cpu_dout;
                        if (cpu_addr[7:0] == `P1_DATA_REG)       p1reg <= cpu_dout;
                        if (cpu_addr[7:0] == `P1_DIR_REG)        p1dir <= cpu_dout;
                        if (cpu_addr[7:0] == `P1_DIR_REG)        p1dir <= cpu_dout;
                        if (cpu_addr[7:0] == `P2_DATA_REG)       p2reg <= cpu_dout;
                        if (cpu_addr[7:0] == `P2_DATA_REG)       p2reg <= cpu_dout;
                        if (cpu_addr[7:0] == `P2_DIR_REG)        p2dir <= cpu_dout;
                        if (cpu_addr[7:0] == `P2_DIR_REG)        p2dir <= cpu_dout;
 
                        if (cpu_addr[7:0] == `INTR_EN_REG)       intr_ena <= cpu_dout[3:0];
                end
                end
 
 
                // receiver full flag 
                // receiver full flag 
                if (rxValid && !rxfull)
                if (rxValid && !rxfull)
                        rxfull <= 1'b1;
                        rxfull <= 1'b1;
Line 164... Line 171...
                // sampled io control to select cpu data input 
                // sampled io control to select cpu data input 
                scpu_io <= cpu_io;
                scpu_io <= cpu_io;
        end
        end
end
end
 
 
 
// interrupt controller 
 
intr_ctrl intrc
 
(
 
        .clock(clock),
 
        .reset(reset),
 
        .ext_intr(extint),
 
        .cpu_intr(cpu_intr),
 
        .cpu_inte(cpu_inte),
 
        .cpu_inta(cpu_inta),
 
        .cpu_rd(cpu_rd),
 
        .cpu_inst(intr_dout),
 
        .intr_ena(intr_ena)
 
);
 
 
// uart module mapped to the io space 
// uart module mapped to the io space 
uart uart
uart uart
(
(
        .clock(clock),
        .clock(clock),
        .reset(reset),
        .reset(reset),

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.