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Line 47... |
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
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set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
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set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
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set_global_assignment -name SEARCH_PATH ..\\..\\rtl\\verilog\\cores\\rs/
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set_global_assignment -name SEARCH_PATH ..\\..\\rtl\\verilog\\cores\\rs/
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set_global_assignment -name SEARCH_PATH "c:\\altera\\81\\ip\\altera\\reed_solomon\\lib/"
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set_global_assignment -name SEARCH_PATH "c:\\altera\\81\\ip\\altera\\reed_solomon\\lib/"
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set_global_assignment -name SEARCH_PATH ..\\..\\rtl\\verilog/
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set_global_assignment -name SEARCH_PATH ..\\..\\rtl\\verilog/
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set_global_assignment -name VERILOG_FILE ../../rtl/l80soc.v
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set_global_assignment -name VERILOG_FILE ../../rtl/light8080.v
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set_global_assignment -name VERILOG_FILE ../../rtl/micro_rom.v
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set_global_assignment -name VERILOG_FILE ../../rtl/ram_image.v
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set_global_assignment -name VERILOG_FILE ../../rtl/uart.v
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
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set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
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set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
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set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
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set_global_assignment -name USE_CONFIGURATION_DEVICE ON
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set_global_assignment -name USE_CONFIGURATION_DEVICE ON
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set_global_assignment -name FMAX_REQUIREMENT "15 ns"
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set_global_assignment -name FMAX_REQUIREMENT "15 ns"
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set_global_assignment -name VERILOG_FILE ../../rtl/l80soc.v
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set_global_assignment -name VERILOG_FILE ../../rtl/intr_ctrl.v
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set_global_assignment -name VERILOG_FILE ../../rtl/light8080.v
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set_global_assignment -name VERILOG_FILE ../../rtl/micro_rom.v
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set_global_assignment -name VERILOG_FILE ../../rtl/ram_image.v
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set_global_assignment -name VERILOG_FILE ../../rtl/uart.v
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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