OpenCores
URL https://opencores.org/ocsvn/light8080/light8080/trunk

Subversion Repositories light8080

[/] [light8080/] [trunk/] [verilog/] [syn/] [altera_c2/] [l80soc.qsf] - Diff between revs 65 and 66

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 65 Rev 66
Line 47... Line 47...
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name SEARCH_PATH ..\\..\\rtl\\verilog\\cores\\rs/
set_global_assignment -name SEARCH_PATH ..\\..\\rtl\\verilog\\cores\\rs/
set_global_assignment -name SEARCH_PATH "c:\\altera\\81\\ip\\altera\\reed_solomon\\lib/"
set_global_assignment -name SEARCH_PATH "c:\\altera\\81\\ip\\altera\\reed_solomon\\lib/"
set_global_assignment -name SEARCH_PATH ..\\..\\rtl\\verilog/
set_global_assignment -name SEARCH_PATH ..\\..\\rtl\\verilog/
set_global_assignment -name VERILOG_FILE ../../rtl/l80soc.v
 
set_global_assignment -name VERILOG_FILE ../../rtl/light8080.v
 
set_global_assignment -name VERILOG_FILE ../../rtl/micro_rom.v
 
set_global_assignment -name VERILOG_FILE ../../rtl/ram_image.v
 
set_global_assignment -name VERILOG_FILE ../../rtl/uart.v
 
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name FMAX_REQUIREMENT "15 ns"
set_global_assignment -name FMAX_REQUIREMENT "15 ns"
 
set_global_assignment -name VERILOG_FILE ../../rtl/l80soc.v
 
set_global_assignment -name VERILOG_FILE ../../rtl/intr_ctrl.v
 
set_global_assignment -name VERILOG_FILE ../../rtl/light8080.v
 
set_global_assignment -name VERILOG_FILE ../../rtl/micro_rom.v
 
set_global_assignment -name VERILOG_FILE ../../rtl/ram_image.v
 
set_global_assignment -name VERILOG_FILE ../../rtl/uart.v
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
 No newline at end of file
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.