| Line 733... |
Line 733... |
signal do_cpc_d : std_logic; -- do_cpc, pipelined
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signal do_cpc_d : std_logic; -- do_cpc, pipelined
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signal do_daa : std_logic; -- ALU operation is DAA
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signal do_daa : std_logic; -- ALU operation is DAA
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signal clear_cy : std_logic; -- Instruction unconditionally clears CY
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signal clear_cy : std_logic; -- Instruction unconditionally clears CY
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signal clear_ac : std_logic; -- Instruction unconditionally clears AC
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signal clear_ac : std_logic; -- Instruction unconditionally clears AC
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signal set_ac : std_logic; -- Instruction unconditionally sets AC
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signal set_ac : std_logic; -- Instruction unconditionally sets AC
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signal flag_ac : std_logic; -- new computed half carry flag
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signal flag_ac : std_logic; -- New computed half carry (AC) flag
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signal flag_ac_daa : std_logic; -- AC flag computed in the special case of DAA
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signal flag_ac_and : std_logic; -- AC flag computed in the special case of AN*
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-- flag_aux_cy: new computed half carry flag (used in 16-bit ops)
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-- flag_aux_cy: new computed half carry flag (used in 16-bit ops)
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signal flag_aux_cy : std_logic;
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signal flag_aux_cy : std_logic;
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signal load_psw : std_logic; -- load F register
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signal load_psw : std_logic; -- load F register
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-- aux carry computation and control signals
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-- aux carry computation and control signals
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| Line 760... |
Line 762... |
signal arith_op2_sgn: std_logic_vector(8 downto 0);
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signal arith_op2_sgn: std_logic_vector(8 downto 0);
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signal arith_res : std_logic_vector(8 downto 0);
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signal arith_res : std_logic_vector(8 downto 0);
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signal arith_res8 : std_logic_vector(7 downto 0);
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signal arith_res8 : std_logic_vector(7 downto 0);
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-- ALU DAA intermediate signals (DAA has fully dedicated logic)
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-- ALU DAA intermediate signals (DAA has fully dedicated logic)
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signal daa_res : std_logic_vector(8 downto 0);
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signal daa_res8 : std_logic_vector(7 downto 0);
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signal daa_res9 : std_logic_vector(8 downto 0);
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signal daa_res9 : std_logic_vector(8 downto 0);
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signal daa_test1 : std_logic;
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signal daa_test1 : std_logic;
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signal daa_test1a : std_logic;
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signal daa_test1a : std_logic;
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signal daa_test2 : std_logic;
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signal daa_test2 : std_logic;
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signal daa_test2a : std_logic;
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signal daa_test2a : std_logic;
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signal arith_daa_res :std_logic_vector(7 downto 0);
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signal arith_daa_res :std_logic_vector(7 downto 0);
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signal cy_daa : std_logic;
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signal cy_daa : std_logic;
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signal acc_low_gt9 : std_logic;
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signal acc_high_gt9 : std_logic;
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signal acc_high_ge9 : std_logic;
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signal daa_adjust : std_logic_vector(8 downto 0);
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-- ALU CY flag intermediate signals
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-- ALU CY flag intermediate signals
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signal cy_in_sgn : std_logic;
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signal cy_in_sgn : std_logic;
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signal cy_in : std_logic;
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signal cy_in : std_logic;
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signal cy_in_gated : std_logic;
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signal cy_in_gated : std_logic;
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| Line 839... |
Line 843... |
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load_al <= ucode(24);
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load_al <= ucode(24);
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load_addr <= ucode(25);
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load_addr <= ucode(25);
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do_cy_op_d <= '1' when ucode(5 downto 2)="1011" else '0'; -- decode CY ALU op
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do_cy_op_d <= '1' when ucode(5 downto 2)="1011" else '0'; -- decode CY ALU op
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do_cpc_d <= ucode(0); -- decode CPC ALU op
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do_cpc_d <= ucode(0); -- decode CPC ALU op; valid only when do_cy_op_d='1'
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-- uinst jump command, either unconditional or on a given condition
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-- uinst jump command, either unconditional or on a given condition
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uc_do_jmp <= uc_jsr or (uc_tjsr and condition_reg);
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uc_do_jmp <= uc_jsr or (uc_tjsr and condition_reg);
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vma <= load_addr; -- addr is valid, either for memmory or io
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vma <= load_addr; -- addr is valid, either for memmory or io
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| Line 1175... |
Line 1179... |
-- take only 8 bits; 9th bit of adder is cy output
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-- take only 8 bits; 9th bit of adder is cy output
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arith_res8 <= arith_res(7 downto 0);
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arith_res8 <= arith_res(7 downto 0);
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cy_adder <= arith_res(8);
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cy_adder <= arith_res(8);
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--##### DAA dedicated logic
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--##### DAA dedicated logic
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-- Note a DAA takes 2 cycles to complete!
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-- Intel documentation does not cover many details of this instruction.
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-- It has been experimentally determined that the following is the algorithm
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-- employed in the actual original silicon:
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--
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-- 1.- If ACC(3..0) > 9 OR AC=1 then add 06h to ACC.
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-- 2.- If (ACC(7..4) > 9 OR AC=1) OR (ACC(7..4)==9 AND (CY=1 OR ACC(3..0) > 9))
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-- then add 60h to ACC.
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-- Steps 1 and 2 are performed in parallel.
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-- AC = 1 iif ACC(3..0) >= 10
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-- CY = 1 if CY was already 1 OR
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-- (ACC(7..4)>=9 AND ACC(3..0)>=10) OR
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-- ACC(7..4)>=10
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-- else CY is zero.
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-- Note a DAA takes 2 cycles to complete; the adjutment addition is registered
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-- so that it does not become the speed bottleneck. The DAA microcode will
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-- execute two ALU DAA operations in a row before taking the ALU result.
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-- '1' when ACC(3..0) > 9
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acc_low_gt9 <= '1' when
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conv_integer(arith_op2(3 downto 0)) > 9
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--arith_op2(3 downto 2)="11" or arith_op2(3 downto 1)="101"
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else '0';
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-- '1' when ACC(7..4) > 9
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acc_high_gt9 <= '1' when
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conv_integer(arith_op2(7 downto 4)) > 9
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--arith_op2(7 downto 6)="11" or arith_op2(7 downto 5)="101"
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else '0';
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-- '1' when ACC(7..4) >= 9
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acc_high_ge9 <= '1' when
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conv_integer(arith_op2(7 downto 4)) >= 9
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else '0';
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-- Condition for adding 6 to the low nibble
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daa_test1 <= '1' when
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acc_low_gt9='1' or -- A(3..0) > 9
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flag_reg(4)='1' -- AC set
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else '0';
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-- condition for adding 6 to the high nibble
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daa_test2 <= '1' when
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(acc_high_gt9='1' or -- A(7..4) > 9
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flag_reg(0)='1') or -- CY set
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(daa_test2a = '1') -- condition below
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else '0';
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-- A(7..4)==9 && (CY or ACC(3..0)>9)
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daa_test2a <= '1' when
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arith_op2(7 downto 4)="1001" and (flag_reg(0)='1' or acc_low_gt9='1')
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else '0';
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--daa_test1a='1' when daa_res9(7 downto 4) > 0x06
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-- daa_adjust is what we will add to ACC in order to adjust it to BCD
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daa_test1a <= arith_op2(3) and (arith_op2(2) or arith_op2(1) or arith_op2(0));
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daa_adjust(3 downto 0) <= "0110" when daa_test1='1' else "0000";
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daa_test1 <= '1' when flag_reg(4)='1' or daa_test1a='1' else '0';
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daa_adjust(7 downto 4) <= "0110" when daa_test2='1' else "0000";
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daa_adjust(8) <= '0';
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-- The adder is registered so as to improve the clock rate. This takes the DAA
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-- logic out of the critical speed path at the cost of an extra cycle for DAA,
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-- which is a good compromise.
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daa_adjutment_adder:
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process(clk)
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process(clk)
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begin
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begin
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if clk'event and clk='1' then
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if clk'event and clk='1' then
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if reset='1' then
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daa_res9 <= arith_op2 + daa_adjust;
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daa_res9 <= "000000000";
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else
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if daa_test1='1' then
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daa_res9 <= arith_op2 + "000000110";
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else
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daa_res9 <= arith_op2;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process daa_adjutment_adder;
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--daa_test2a='1' when daa_res9(7 downto 4) > 0x06 FIXME unused?
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daa_test2a <= daa_res9(7) and (daa_res9(6) or daa_res9(5) or daa_res9(4));
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daa_test2 <= '1' when flag_reg(0)='1' or daa_test1a='1' else '0';
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daa_res <= '0'&daa_res9(7 downto 0) + "01100000" when daa_test2='1'
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-- AC flag raised if the low nibble was > 9, cleared otherwise.
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else daa_res9;
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flag_ac_daa <= acc_low_gt9;
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cy_daa <= daa_res(8);
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-- CY flag raised if the condition above holds, otherwise keeps current value.
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cy_daa <= '1' when
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flag_reg(0)='1' or -- If CY is already 1, keep value
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( (acc_high_ge9='1' and acc_low_gt9='1') or (acc_low_gt9='1') )
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else '0';
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-- DAA vs. adder mux
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-- DAA vs. adder mux
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arith_daa_res <= daa_res(7 downto 0) when do_daa='1' else arith_res8;
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arith_daa_res <= daa_res9(7 downto 0) when do_daa='1' else arith_res8;
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-- DAA vs. adder CY mux
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-- DAA vs. adder CY mux
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cy_arith <= cy_daa when do_daa='1' else cy_adder;
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cy_arith <= cy_daa when do_daa='1' else cy_adder;
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--##### Logic operations block
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--##### Logic operations block
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| Line 1248... |
Line 1300... |
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flag_s <= alu_output(7);
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flag_s <= alu_output(7);
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flag_p <= not(alu_output(7) xor alu_output(6) xor alu_output(5) xor alu_output(4) xor
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flag_p <= not(alu_output(7) xor alu_output(6) xor alu_output(5) xor alu_output(4) xor
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alu_output(3) xor alu_output(2) xor alu_output(1) xor alu_output(0));
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alu_output(3) xor alu_output(2) xor alu_output(1) xor alu_output(0));
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flag_z <= '1' when alu_output=X"00" else '0';
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flag_z <= '1' when alu_output=X"00" else '0';
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-- AC is either the CY from bit 4 OR 0 if the instruction clears it implicitly
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-- AC is either the CY from bit 4 OR 0 if the instruction clears it implicitly
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flag_ac <= '1' when set_ac = '1' else
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flag_ac <= flag_ac_and when set_ac = '1' and do_daa='0' else
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'0' when clear_ac = '1' else
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'0' when clear_ac = '1' else
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flag_ac_daa when do_daa = '1' else
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(arith_op1(4) xor arith_op2_sgn(4) xor alu_output(4));
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(arith_op1(4) xor arith_op2_sgn(4) xor alu_output(4));
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-- AN* instructions deal with AC flag a bit differently
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flag_ac_and <= T1(3) or T2(3);
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-- CY comes from the adder or the shifter, or is 0 if the instruction
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-- CY comes from the adder or the shifter, or is 0 if the instruction
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-- implicitly clears it.
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-- implicitly clears it.
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flag_cy_1 <= '0' when clear_cy = '1' else
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flag_cy_1 <= '0' when clear_cy = '1' else
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cy_arith when use_logic = '1' and clear_cy = '0' else
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cy_arith when use_logic = '1' and clear_cy = '0' else
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cy_shifter;
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cy_shifter;
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-- CY can also be explicitly set or complemented by STC and CMC
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flag_cy_2 <= not flag_reg(0) when do_cpc='0' else '1'; -- cmc, stc
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flag_cy_2 <= not flag_reg(0) when do_cpc='0' else '1'; -- cmc, stc
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-- No do the actual CY update
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flag_cy <= flag_cy_1 when do_cy_op='0' else flag_cy_2;
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flag_cy <= flag_cy_1 when do_cy_op='0' else flag_cy_2;
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flag_aux_cy <= cy_adder;
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flag_aux_cy <= cy_adder;
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-- auxiliary carry reg
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-- auxiliary carry reg
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