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--##############################################################################
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--##############################################################################
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-- light8080 core
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-- light8080 : Intel 8080 binary compatible core
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--##############################################################################
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--##############################################################################
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-- v1.0 (05 nov 2007) Jose A. Ruiz
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-- v1.1 (20 sep 2008) Microcode bug in INR fixed.
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-- This file and all the light8080 project is freeware (See COPYING.TXT)
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-- v1.0 (05 nov 2007) First release. Jose A. Ruiz.
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--
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-- This file and all the light8080 project are freeware (See COPYING.TXT)
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--##############################################################################
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-- -- (More comprehensive explainations can be found in the design notes)
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--##############################################################################
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--##############################################################################
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic );
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reset : in std_logic );
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end light8080;
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end light8080;
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--##############################################################################
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--##############################################################################
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-- All memory and io accesses are synchronous. Signal vma works as the master
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-- All memory and io accesses are synchronous (rising clock edge). Signal vma
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-- memory and io synchronous enable. More specifically:
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-- works as the master memory and io synchronous enable. More specifically:
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--
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--
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-- * All memory/io control signals (io,rd,wr) are valid only when vma is
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-- * All memory/io control signals (io,rd,wr) are valid only when vma is
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-- high. They never activate when vms is inactive.
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-- high. They never activate when vms is inactive.
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-- * Signals data_out and address are only valid when vma='1'. The high
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-- * Signals data_out and address are only valid when vma='1'. The high
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-- address byte is 0x00 fir all io accesses.
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-- address byte is 0x00 for all io accesses.
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-- * Signal data_in should be valid by the end of the cycle after vma='1'.
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-- * Signal data_in should be valid by the end of the cycle after vma='1',
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-- data is clocked in by the rising clock edge.
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--
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-- All signals are assumed to be synchronous to the master clock. Prevention of
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-- metastability, if necessary, is up to you.
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--
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--
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-- Signal reset needs to be active for 1 clock cycle (i.e. it is sampled on a
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-- Signal reset needs to be active for just 1 clock cycle (it is sampled on a
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-- positive clock edge and is subject to setup and hold times).
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-- positive clock edge and is subject to setup and hold times).
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-- Once reset is deasserted, the first fetch at address 0x0000 will happen 4
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-- Once reset is deasserted, the first fetch at address 0x0000 will happen 4
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-- cycles later.
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-- cycles later.
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--
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--
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-- Signal intr is sampled on all positive clock edges. If asserted when inte is
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-- Signal intr is sampled on all positive clock edges. If asserted when inte is
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-- high, interrupts will be disabled, inta will be asserted high and a fetch
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-- high, interrupts will be disabled, inta will be asserted high and a fetch
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-- cycle will occur. The fetched instruction will be executed normally, except
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-- cycle will occur. The fetched instruction will be executed normally, except
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-- PC will not be valid in any subsequent fetch cycles of the same instruction,
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-- PC will not be valid in any subsequent fetch cycles of the same instruction,
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-- and will not be incremented.
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-- and will not be incremented (In practice, the same as the original 8080).
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-- inta will remain high for the duration of the fetched instruction (in the
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-- inta will remain high for the duration of the fetched instruction (in the
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-- original 8080 it was high only for the opcode fetch cycle).
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-- original 8080 it was high only for the opcode fetch cycle).
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-- PC will not be incremented while inta is high, but it can be explicitly
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-- PC will not be autoincremented while inta is high, but it can be explicitly
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-- modified (e.g. RTS, CALL, etc.).
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-- modified (e.g. RTS, CALL, etc.). Again, the same as the original.
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-- Interrupts will be disabled upon assertion of inta, and remain disabled
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-- Interrupts will be disabled upon assertion of inta, and remain disabled
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-- until explicitly enabled by the program (as in the original).
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-- until explicitly enabled by the program (as in the original).
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--
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--
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-- The above means that any instruction can be supplied in an inta cycle,
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-- The above means that any instruction can be supplied in an inta cycle,
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-- single byte or multibyte. See the design notes.
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-- either single byte or multibyte. See the design notes.
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--##############################################################################
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--##############################################################################
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architecture microcoded of light8080 is
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architecture microcoded of light8080 is
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-- addr_low: low byte of address
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-- addr_low: low byte of address
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