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-- light8080 : Intel 8080 binary compatible core
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-- light8080 : Intel 8080 binary compatible core
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--##############################################################################
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--##############################################################################
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-- v1.1 (20 sep 2008) Microcode bug in INR fixed.
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-- v1.1 (20 sep 2008) Microcode bug in INR fixed.
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-- v1.0 (05 nov 2007) First release. Jose A. Ruiz.
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-- v1.0 (05 nov 2007) First release. Jose A. Ruiz.
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--
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--
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-- This file and all the light8080 project are freeware (See COPYING.TXT)
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-- This file and all the light8080 project files are freeware (See COPYING.TXT)
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--##############################################################################
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--##############################################################################
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-- -- (More comprehensive explainations can be found in the design notes)
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-- (See timing diagrams at bottom of file. More comprehensive explainations can
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-- be found in the design notes)
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--##############################################################################
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--##############################################################################
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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-- inte : interrupt status (1 when enabled)
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-- inte : interrupt status (1 when enabled)
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-- intr : interrupt request
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-- intr : interrupt request
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-- inta : interrupt acknowledge
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-- inta : interrupt acknowledge
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-- reset : synchronous reset
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-- reset : synchronous reset
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-- clk : clock
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-- clk : clock
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--
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-- (see timing diagrams at bottom of file)
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--##############################################################################
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--##############################################################################
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entity light8080 is
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entity light8080 is
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Port (
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Port (
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addr_out : out std_logic_vector(15 downto 0);
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addr_out : out std_logic_vector(15 downto 0);
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inta : out std_logic;
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inta : out std_logic;
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Line 43... |
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vma : out std_logic;
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vma : out std_logic;
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io : out std_logic;
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io : out std_logic;
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rd : out std_logic;
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rd : out std_logic;
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wr : out std_logic;
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wr : out std_logic;
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fetch : out std_logic;
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data_in : in std_logic_vector(7 downto 0);
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data_in : in std_logic_vector(7 downto 0);
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data_out : out std_logic_vector(7 downto 0);
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data_out : out std_logic_vector(7 downto 0);
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic );
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reset : in std_logic );
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-- uinst jump command, either unconditional or on a given condition
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-- uinst jump command, either unconditional or on a given condition
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uc_do_jmp <= uc_jsr or (uc_tjsr and condition_reg);
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uc_do_jmp <= uc_jsr or (uc_tjsr and condition_reg);
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vma <= load_addr; -- addr is valid, either for memmory or io
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vma <= load_addr; -- addr is valid, either for memmory or io
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-- assume the only uinst that does memory access in the range 0..f is 'fetch'
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fetch <= '1' when uc_addr(7 downto 4)=X"0" and load_addr='1' else '0';
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-- external bus interface control signals
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-- external bus interface control signals
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io <= '1' when uc_flags1="100" else '0'; -- IO access (vs. memory)
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io <= '1' when uc_flags1="100" else '0'; -- IO access (vs. memory)
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rd <= '1' when uc_flags2="101" else '0'; -- RD access
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rd <= '1' when uc_flags2="101" else '0'; -- RD access
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wr <= '1' when uc_flags2="110" else '0'; -- WR access
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wr <= '1' when uc_flags2="110" else '0'; -- WR access
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Line 944... |
begin
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begin
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if clk'event and clk='1' then
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if clk'event and clk='1' then
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if reset = '1' then
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if reset = '1' then
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int_pending <= '0';
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int_pending <= '0';
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else
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else
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if intr = '1' and inte_reg = '1' then
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if intr = '1' and inte_reg = '1' and int_pending = '0' then
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int_pending <= '1';
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int_pending <= '1';
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else
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else
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if inte_reg = '1' and uc_end='1' then
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if inte_reg = '1' and uc_end='1' then
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int_pending <= '0';
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int_pending <= '0';
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end if;
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end if;
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data_out <= DO;
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data_out <= DO;
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end microcoded;
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end microcoded;
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No newline at end of file
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No newline at end of file
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--------------------------------------------------------------------------------
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-- Timing diagram 1: RD and WR cycles
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--------------------------------------------------------------------------------
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-- 1 2 3 4 5 6 7 8
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-- __ __ __ __ __ __ __ __
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-- clk __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__
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--
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-- addr_o xxxxxxxxxxxxxx< ADR >xxxxxxxxxxx< ADR >xxxxxxxxxxx
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--
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-- data_i xxxxxxxxxxxxxxxxxxxx< Din >xxxxxxxxxxxxxxxxxxxxxxx
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--
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-- data_o xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx< Dout>xxxxxxxxxxx
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-- _____ _____
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-- vma_o ______________/ \___________/ \___________
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-- _____
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-- rd_o ______________/ \_____________________________
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-- _____
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-- wr_o ________________________________/ \___________
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--
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-- (functional diagram, actual time delays not shown)
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--------------------------------------------------------------------------------
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-- This diagram shows a read cycle and a write cycle back to back.
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-- In clock edges (4) and (7), the address is loaded into the external
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-- synchronous RAM address register.
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-- In clock edge (5), read data is loaded into the CPU.
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-- In clock edge (7), write data is loaded into the external synchronous RAM.
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-- In actual operation, the CPU does about 1 rd/wr cycle for each 5 clock
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-- cycles, which is a waste of RAM bandwidth.
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--
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No newline at end of file
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No newline at end of file
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