| Line 147... |
Line 147... |
signal uc_do_ret : std_logic; -- ret flag, pipelined
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signal uc_do_ret : std_logic; -- ret flag, pipelined
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signal uc_halt_flag : std_logic; -- uinst field, decoded 'halt' flag
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signal uc_halt_flag : std_logic; -- uinst field, decoded 'halt' flag
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signal uc_halt : std_logic; -- halt command
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signal uc_halt : std_logic; -- halt command
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signal halt_reg : std_logic; -- halt status reg, output as 'halt' signal
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signal halt_reg : std_logic; -- halt status reg, output as 'halt' signal
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signal uc_ei : std_logic; -- uinst field, decoded 'ei' flag
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signal uc_ei : std_logic; -- uinst field, decoded 'ei' flag
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signal uc_di : std_logic; -- uinst field, decoded 'ei' flag
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signal uc_di : std_logic; -- uinst field, decoded 'di' flag
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signal inte_reg : std_logic; -- inte status reg, output as 'inte' signal
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signal inte_reg : std_logic; -- inte status reg, output as 'inte' signal
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signal int_pending : std_logic; -- intr requested, inta not active yet
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signal int_pending : std_logic; -- intr requested, inta not active yet
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signal inta_reg : std_logic; -- inta status reg, output as 'inta'
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signal inta_reg : std_logic; -- inta status reg, output as 'inta'
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signal clr_t1 : std_logic; -- uinst field, explicitly erase T1
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signal clr_t1 : std_logic; -- uinst field, explicitly erase T1
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signal do_clr_t1 : std_logic; -- clr_t1 pipelined
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signal do_clr_t1 : std_logic; -- clr_t1 pipelined
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signal clr_t2 : std_logic; -- uinst field, explicitly erase T2
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signal clr_t2 : std_logic; -- uinst field, explicitly erase T2
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signal do_clr_t2 : std_logic; -- clr_t2 pipelined
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signal do_clr_t2 : std_logic; -- clr_t2 pipelined
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signal ucode : std_logic_vector(31 downto 0); -- microcode word
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signal ucode : std_logic_vector(31 downto 0); -- microcode word
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signal ucode_field2 : std_logic_vector(24 downto 0); -- pipelined microcode
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signal ucode_field2 : std_logic_vector(24 downto 0); -- pipelined microcode
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-- used to delay interrup enable for one entire instruction after EI
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signal delayed_ei : std_logic;
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-- microcode ROM : see design notes and microcode source file
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-- microcode ROM : see design notes and microcode source file
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type t_rom is array (0 to 511) of std_logic_vector(31 downto 0);
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type t_rom is array (0 to 511) of std_logic_vector(31 downto 0);
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signal rom : t_rom := (
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signal rom : t_rom := (
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"00000000000000000000000000000000", -- 000
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"00000000000000000000000000000000", -- 000
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| Line 772... |
Line 775... |
-- ALU intermediate results
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-- ALU intermediate results
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signal logic_res : std_logic_vector(7 downto 0);
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signal logic_res : std_logic_vector(7 downto 0);
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signal shift_res : std_logic_vector(7 downto 0);
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signal shift_res : std_logic_vector(7 downto 0);
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signal alu_mux1 : std_logic_vector(7 downto 0);
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signal alu_mux1 : std_logic_vector(7 downto 0);
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begin
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begin
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DI <= data_in;
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DI <= data_in;
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process(clk) -- IR register, load when uc_decode flag activates
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process(clk) -- IR register, load when uc_decode flag activates
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| Line 935... |
Line 939... |
process(clk)
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process(clk)
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begin
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begin
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if clk'event and clk='1' then
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if clk'event and clk='1' then
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if reset = '1' then
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if reset = '1' then
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inte_reg <= '0';
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inte_reg <= '0';
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delayed_ei <= '0';
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else
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if (uc_di='1' or uc_ei='1') and uc_end='1' then
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--inte_reg <= uc_ei;
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delayed_ei <= uc_ei; -- FIXME DI must not be delayed
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end if;
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if uc_end = '1' then -- at the last cycle of every instruction...
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if uc_di='1' then -- ...disable interrupts if the instruction is DI...
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inte_reg <= '0';
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else
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else
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if uc_di='1' or uc_ei='1' then
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-- ...of enable interrupts after the instruction following EI
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inte_reg <= uc_ei;
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inte_reg <= delayed_ei;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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