Subversion Repositories light8080

--##############################################################################

--##############################################################################

-- light8080 : Intel 8080 binary compatible core

-- light8080 : Intel 8080 binary compatible core

--##############################################################################

--##############################################################################

-- v1.1    (20 sep 2008) Microcode bug in INR fixed.

-- v1.1    (20 sep 2008) Microcode bug in INR fixed.

-- v1.0    (05 nov 2007) First release. Jose A. Ruiz.

-- v1.0    (05 nov 2007) First release. Jose A. Ruiz.

--

--

-- This file and all the light8080 project files are freeware (See COPYING.TXT)

-- This file and all the light8080 project files are freeware (See COPYING.TXT)

--##############################################################################

--##############################################################################

signal do_cy_op :     std_logic; -- ALU explicit CY operation (CPC, etc.)

signal do_cy_op :     std_logic; -- ALU explicit CY operation (CPC, etc.)

signal do_cy_op_d :   std_logic; -- do_cy_op, pipelined

signal do_cy_op_d :   std_logic; -- do_cy_op, pipelined

signal do_cpc :       std_logic; -- ALU operation is CPC

signal do_cpc :       std_logic; -- ALU operation is CPC

signal do_cpc_d :     std_logic; -- do_cpc, pipelined

signal do_cpc_d :     std_logic; -- do_cpc, pipelined

signal do_daa :       std_logic; -- ALU operation is DAA

signal do_daa :       std_logic; -- ALU operation is DAA

signal flag_ac :      std_logic; -- new computed half carry flag

signal flag_ac :      std_logic; -- new computed half carry flag

-- flag_aux_cy: new computed half carry flag (used in 16-bit ops)

-- flag_aux_cy: new computed half carry flag (used in 16-bit ops)

signal flag_aux_cy :  std_logic;

signal flag_aux_cy :  std_logic;

signal load_psw :     std_logic; -- load F register

signal load_psw :     std_logic; -- load F register

flag_pattern <=  ucode_field2(9 downto 8);

flag_pattern <=  ucode_field2(9 downto 8);

use_aux_cy <= ucode_field2(19);

use_aux_cy <= ucode_field2(19);

do_cpc <= ucode_field2(23);

do_cpc <= ucode_field2(23);

do_cy_op <= ucode_field2(24);

do_cy_op <= ucode_field2(24);

do_daa <= '1' when ucode_field2(5 downto 2) = "1010" else '0';

do_daa <= '1' when ucode_field2(5 downto 2) = "1010" else '0';

aux_cy_in <= reg_aux_cy when set_aux_cy = '0' else '1';

aux_cy_in <= reg_aux_cy when set_aux_cy = '0' else '1';

-- carry input selection: normal or aux (for 16 bit increments)?

-- carry input selection: normal or aux (for 16 bit increments)?

cy_in <= flag_reg(0) when use_aux_cy = '0' else aux_cy_in;

cy_in <= flag_reg(0) when use_aux_cy = '0' else aux_cy_in;

flag_s <= alu_output(7);

flag_s <= alu_output(7);

flag_p <= not(alu_output(7) xor alu_output(6) xor alu_output(5) xor alu_output(4) xor

flag_p <= not(alu_output(7) xor alu_output(6) xor alu_output(5) xor alu_output(4) xor

         alu_output(3) xor alu_output(2) xor alu_output(1) xor alu_output(0));

         alu_output(3) xor alu_output(2) xor alu_output(1) xor alu_output(0));

flag_z <= '1' when alu_output=X"00" else '0';

flag_z <= '1' when alu_output=X"00" else '0';

flag_cy_2 <= not flag_reg(0) when do_cpc='0' else '1'; -- cmc, stc

flag_cy_2 <= not flag_reg(0) when do_cpc='0' else '1'; -- cmc, stc

flag_cy <= flag_cy_1 when do_cy_op='0' else flag_cy_2;

flag_cy <= flag_cy_1 when do_cy_op='0' else flag_cy_2;

flag_aux_cy <= cy_adder;

flag_aux_cy <= cy_adder;