| Line 1... |
Line 1... |
--##############################################################################
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--##############################################################################
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-- light8080 : Intel 8080 binary compatible core
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-- light8080 : Intel 8080 binary compatible core
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--##############################################################################
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--##############################################################################
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-- v1.3 (12 FEB 2012) Fix: General solution to AND, OR, XOR clearing CY,ACY.
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-- v1.2 (08 jul 2010) Fix: XOR operations were not clearing CY,ACY.
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-- v1.2 (08 jul 2010) Fix: XOR operations were not clearing CY,ACY.
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-- v1.1 (20 sep 2008) Microcode bug in INR fixed.
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-- v1.1 (20 sep 2008) Microcode bug in INR fixed.
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-- v1.0 (05 nov 2007) First release. Jose A. Ruiz.
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-- v1.0 (05 nov 2007) First release. Jose A. Ruiz.
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--
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--
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-- This file and all the light8080 project files are freeware (See COPYING.TXT)
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-- This file and all the light8080 project files are freeware (See COPYING.TXT)
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| Line 57... |
Line 58... |
--##############################################################################
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--##############################################################################
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-- All memory and io accesses are synchronous (rising clock edge). Signal vma
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-- All memory and io accesses are synchronous (rising clock edge). Signal vma
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-- works as the master memory and io synchronous enable. More specifically:
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-- works as the master memory and io synchronous enable. More specifically:
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--
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--
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-- * All memory/io control signals (io,rd,wr) are valid only when vma is
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-- * All memory/io control signals (io,rd,wr) are valid only when vma is
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-- high. They never activate when vms is inactive.
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-- high. They never activate when vma is inactive.
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-- * Signals data_out and address are only valid when vma='1'. The high
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-- * Signals data_out and address are only valid when vma='1'. The high
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-- address byte is 0x00 for all io accesses.
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-- address byte is 0x00 for all io accesses.
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-- * Signal data_in should be valid by the end of the cycle after vma='1',
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-- * Signal data_in should be valid by the end of the cycle after vma='1',
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-- data is clocked in by the rising clock edge.
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-- data is clocked in by the rising clock edge.
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--
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--
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| Line 231... |
Line 232... |
"00001000000000000000110000011111", -- 03c
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"00001000000000000000110000011111", -- 03c
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"00000100011000111000001101001110", -- 03d
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"00000100011000111000001101001110", -- 03d
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"00001000000000000000110000011111", -- 03e
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"00001000000000000000110000011111", -- 03e
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"00000100011000111000001101001111", -- 03f
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"00000100011000111000001101001111", -- 03f
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"00001000000000000000110000011111", -- 040
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"00001000000000000000110000011111", -- 040
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"00000100011000111000001101000100", -- 041
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"00000100011000111100001101000100", -- 041
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"00001000000000000000110000011111", -- 042
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"00001000000000000000110000011111", -- 042
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"00000100011000111000001101000101", -- 043
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"00000100011000111100001101000101", -- 043
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"00001000000000000000110000011111", -- 044
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"00001000000000000000110000011111", -- 044
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"00000100011000111000001101000110", -- 045
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"00000100011000111100001101000110", -- 045
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"00001000000000000000110000011111", -- 046
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"00001000000000000000110000011111", -- 046
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"00000100011000111000001110001110", -- 047
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"00000100011000111000001110001110", -- 047
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"00000000101010000000000000000000", -- 048
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"00000000101010000000000000000000", -- 048
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"00000100011000111000001101001100", -- 049
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"00000100011000111000001101001100", -- 049
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"00000000101010000000000000000000", -- 04a
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"00000000101010000000000000000000", -- 04a
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| Line 247... |
Line 248... |
"00000000101010000000000000000000", -- 04c
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"00000000101010000000000000000000", -- 04c
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"00000100011000111000001101001110", -- 04d
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"00000100011000111000001101001110", -- 04d
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"00000000101010000000000000000000", -- 04e
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"00000000101010000000000000000000", -- 04e
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"00000100011000111000001101001111", -- 04f
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"00000100011000111000001101001111", -- 04f
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"00000000101010000000000000000000", -- 050
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"00000000101010000000000000000000", -- 050
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"00000100011000111000001101000100", -- 051
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"00000100011000111100001101000100", -- 051
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"00000000101010000000000000000000", -- 052
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"00000000101010000000000000000000", -- 052
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"00000100011000111000001101000101", -- 053
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"00000100011000111100001101000101", -- 053
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"00000000101010000000000000000000", -- 054
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"00000000101010000000000000000000", -- 054
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"00000100011000111000001101000110", -- 055
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"00000100011000111100001101000110", -- 055
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"00000000101010000000000000000000", -- 056
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"00000000101010000000000000000000", -- 056
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"00000100011000111000001110001110", -- 057
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"00000100011000111000001110001110", -- 057
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"00001000000000000000110000011001", -- 058
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"00001000000000000000110000011001", -- 058
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"00000100011000111000001101001100", -- 059
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"00000100011000111000001101001100", -- 059
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"00001000000000000000110000011001", -- 05a
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"00001000000000000000110000011001", -- 05a
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| Line 263... |
Line 264... |
"00001000000000000000110000011001", -- 05c
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"00001000000000000000110000011001", -- 05c
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"00000100011000111000001101001110", -- 05d
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"00000100011000111000001101001110", -- 05d
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"00001000000000000000110000011001", -- 05e
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"00001000000000000000110000011001", -- 05e
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"00000100011000111000001101001111", -- 05f
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"00000100011000111000001101001111", -- 05f
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"00001000000000000000110000011001", -- 060
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"00001000000000000000110000011001", -- 060
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"00000100011000111000001101000100", -- 061
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"00000100011000111100001101000100", -- 061
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"00001000000000000000110000011001", -- 062
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"00001000000000000000110000011001", -- 062
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"00000100011000111000001101000101", -- 063
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"00000100011000111100001101000101", -- 063
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"00001000000000000000110000011001", -- 064
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"00001000000000000000110000011001", -- 064
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"00000100011000111000001101000110", -- 065
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"00000100011000111100001101000110", -- 065
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"00001000000000000000110000011001", -- 066
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"00001000000000000000110000011001", -- 066
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"00000100011000111000001110001110", -- 067
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"00000100011000111000001110001110", -- 067
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"10111100101100000000001001001101", -- 068
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"10111100101100000000001001001101", -- 068
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"00000100000000000000000000000000", -- 069
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"00000100000000000000000000000000", -- 069
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"00001000000000000000110000011001", -- 06a
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"00001000000000000000110000011001", -- 06a
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| Line 707... |
Line 708... |
signal inhibit_pc_increment : std_logic; -- avoid PC changes (during INTA)
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signal inhibit_pc_increment : std_logic; -- avoid PC changes (during INTA)
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signal rbank_rd_addr: std_logic_vector(3 downto 0); -- rbank rd addr
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signal rbank_rd_addr: std_logic_vector(3 downto 0); -- rbank rd addr
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signal rbank_wr_addr: std_logic_vector(3 downto 0); -- rbank wr addr
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signal rbank_wr_addr: std_logic_vector(3 downto 0); -- rbank wr addr
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signal DO : std_logic_vector(7 downto 0); -- data output reg
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signal DO : std_logic_vector(7 downto 0); -- data output reg
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-- Register bank as an array of 16 bytes (asynch. LUT ram)
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-- Register bank as an array of 16 bytes.
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-- This will be implemented as asynchronous LUT RAM in those devices where this
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-- feature is available (Xilinx) and as multiplexed registers where it isn't
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-- (Altera).
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type t_reg_bank is array(0 to 15) of std_logic_vector(7 downto 0);
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type t_reg_bank is array(0 to 15) of std_logic_vector(7 downto 0);
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-- Register bank : BC, DE, HL, AF, [PC, XY, ZW, SP]
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-- Register bank : BC, DE, HL, AF, [PC, XY, ZW, SP]
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signal rbank : t_reg_bank;
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signal rbank : t_reg_bank;
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signal flag_reg : std_logic_vector(7 downto 0); -- F register
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signal flag_reg : std_logic_vector(7 downto 0); -- F register
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| Line 726... |
Line 730... |
signal do_cy_op : std_logic; -- ALU explicit CY operation (CPC, etc.)
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signal do_cy_op : std_logic; -- ALU explicit CY operation (CPC, etc.)
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signal do_cy_op_d : std_logic; -- do_cy_op, pipelined
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signal do_cy_op_d : std_logic; -- do_cy_op, pipelined
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signal do_cpc : std_logic; -- ALU operation is CPC
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signal do_cpc : std_logic; -- ALU operation is CPC
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signal do_cpc_d : std_logic; -- do_cpc, pipelined
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signal do_cpc_d : std_logic; -- do_cpc, pipelined
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signal do_daa : std_logic; -- ALU operation is DAA
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signal do_daa : std_logic; -- ALU operation is DAA
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signal do_xor : std_logic; -- ALU operation is some XOR (clears CY)
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signal clear_cy : std_logic; -- Instruction unconditionally clears CY
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signal clear_ac : std_logic; -- Instruction unconditionally clears AC
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signal set_ac : std_logic; -- Instruction unconditionally sets AC
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signal flag_ac : std_logic; -- new computed half carry flag
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signal flag_ac : std_logic; -- new computed half carry flag
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-- flag_aux_cy: new computed half carry flag (used in 16-bit ops)
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-- flag_aux_cy: new computed half carry flag (used in 16-bit ops)
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signal flag_aux_cy : std_logic;
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signal flag_aux_cy : std_logic;
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signal load_psw : std_logic; -- load F register
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signal load_psw : std_logic; -- load F register
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| Line 1122... |
Line 1128... |
flag_pattern <= ucode_field2(9 downto 8);
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flag_pattern <= ucode_field2(9 downto 8);
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use_aux_cy <= ucode_field2(19);
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use_aux_cy <= ucode_field2(19);
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do_cpc <= ucode_field2(23);
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do_cpc <= ucode_field2(23);
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do_cy_op <= ucode_field2(24);
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do_cy_op <= ucode_field2(24);
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do_daa <= '1' when ucode_field2(5 downto 2) = "1010" else '0';
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do_daa <= '1' when ucode_field2(5 downto 2) = "1010" else '0';
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do_xor <= '1' when ucode_field2(5 downto 0) = "000101" else '0';
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-- ucode_field2(14) will be set for those instructions that modify CY and AC
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-- without following the standard rules -- AND, OR and XOR instructions.
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-- Some instructions will unconditionally clear CY (AND, OR, XOR)
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clear_cy <= ucode_field2(14);
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-- Some instructions will unconditionally clear AC (OR, XOR)...
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clear_ac <= '1' when ucode_field2(14) = '1' and
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ucode_field2(5 downto 0) /= "000100"
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else '0';
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-- ...and some others unconditionally SET AC (AND)
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set_ac <= '1' when ucode_field2(14) = '1' and
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ucode_field2(5 downto 0) = "000100"
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else '0';
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aux_cy_in <= reg_aux_cy when set_aux_cy = '0' else '1';
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aux_cy_in <= reg_aux_cy when set_aux_cy = '0' else '1';
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-- carry input selection: normal or aux (for 16 bit increments)?
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-- carry input selection: normal or aux (for 16 bit increments)?
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cy_in <= flag_reg(0) when use_aux_cy = '0' else aux_cy_in;
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cy_in <= flag_reg(0) when use_aux_cy = '0' else aux_cy_in;
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| Line 1228... |
Line 1248... |
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flag_s <= alu_output(7);
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flag_s <= alu_output(7);
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flag_p <= not(alu_output(7) xor alu_output(6) xor alu_output(5) xor alu_output(4) xor
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flag_p <= not(alu_output(7) xor alu_output(6) xor alu_output(5) xor alu_output(4) xor
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alu_output(3) xor alu_output(2) xor alu_output(1) xor alu_output(0));
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alu_output(3) xor alu_output(2) xor alu_output(1) xor alu_output(0));
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flag_z <= '1' when alu_output=X"00" else '0';
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flag_z <= '1' when alu_output=X"00" else '0';
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-- FIXED 08/JUL/2010: XOR was not clearing AC as it should
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-- AC is either the CY from bit 4 OR 0 if the instruction clears it implicitly
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--flag_ac <= (arith_op1(4) xor arith_op2_sgn(4) xor alu_output(4));
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flag_ac <= '1' when set_ac = '1' else
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flag_ac <= (arith_op1(4) xor arith_op2_sgn(4) xor alu_output(4)) and not do_xor;
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'0' when clear_ac = '1' else
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(arith_op1(4) xor arith_op2_sgn(4) xor alu_output(4));
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-- FIXED 08/JUL/2010: XOR was not clearing CY as it should
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--flag_cy_1 <= cy_arith when use_logic = '1' else cy_shifter;
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-- CY comes from the adder or the shifter, or is 0 if the instruction
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flag_cy_1 <= '0' when do_xor='1' else
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-- implicitly clears it.
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cy_arith when use_logic = '1' and do_xor='0' else
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flag_cy_1 <= '0' when clear_cy = '1' else
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cy_arith when use_logic = '1' and clear_cy = '0' else
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cy_shifter;
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cy_shifter;
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flag_cy_2 <= not flag_reg(0) when do_cpc='0' else '1'; -- cmc, stc
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flag_cy_2 <= not flag_reg(0) when do_cpc='0' else '1'; -- cmc, stc
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flag_cy <= flag_cy_1 when do_cy_op='0' else flag_cy_2;
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flag_cy <= flag_cy_1 when do_cy_op='0' else flag_cy_2;
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flag_aux_cy <= cy_adder;
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flag_aux_cy <= cy_adder;
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