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-- -# Receiver interrupt: Raised when the stop bit is sampled and determined 

-- -# Receiver interrupt: Raised when the stop bit is sampled and determined 

--    to be valid (about the middle of the bit period).

--    to be valid (about the middle of the bit period).

--    If the stop bit is not valid (not high) then the interrupt is not 

--    If the stop bit is not valid (not high) then the interrupt is not 

--    triggered. If a start bit is determined to be spurious (i.e. the falling

--    triggered. If a start bit is determined to be spurious (i.e. the falling

--    edge is detected but the bit value when sampled is not 0) then the

--    edge is detected but the bit value when sampled is not 0) then the

--    This interrupt sets flag RxIrw in the status register.

--    This interrupt sets flag RxIrw in the status register.

-- -# Transmitter interrupt: Raised at the end of the transmission of the stop

-- -# Transmitter interrupt: Raised at the end of the transmission of the stop

--    bit.

--    bit.

--    This interrupt sets flag TxIrq in the status register 1 clock cycle after

--    This interrupt sets flag TxIrq in the status register 1 clock cycle after

--    the interrupt is raised.

--    the interrupt is raised.