OpenCores
URL https://opencores.org/ocsvn/light8080/light8080/trunk

Subversion Repositories light8080

[/] [light8080/] [trunk/] [vhdl/] [soc/] [uart.vhdl] - Diff between revs 70 and 77

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 70 Rev 77
Line 57... Line 57...
-- -# Receiver interrupt: Raised when the stop bit is sampled and determined 
-- -# Receiver interrupt: Raised when the stop bit is sampled and determined 
--    to be valid (about the middle of the bit period).
--    to be valid (about the middle of the bit period).
--    If the stop bit is not valid (not high) then the interrupt is not 
--    If the stop bit is not valid (not high) then the interrupt is not 
--    triggered. If a start bit is determined to be spurious (i.e. the falling
--    triggered. If a start bit is determined to be spurious (i.e. the falling
--    edge is detected but the bit value when sampled is not 0) then the
--    edge is detected but the bit value when sampled is not 0) then the
c
--    interrupt is not triggered.
--    This interrupt sets flag RxIrw in the status register.
--    This interrupt sets flag RxIrw in the status register.
-- -# Transmitter interrupt: Raised at the end of the transmission of the stop
-- -# Transmitter interrupt: Raised at the end of the transmission of the stop
--    bit.
--    bit.
--    This interrupt sets flag TxIrq in the status register 1 clock cycle after
--    This interrupt sets flag TxIrq in the status register 1 clock cycle after
--    the interrupt is raised.
--    the interrupt is raised.

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.