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Line 1... |
--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Light8080 simulation test bench 1 : Interrupt response test
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-- Light8080 simulation test bench 1 : Interrupt response test
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Source for the 8080 program is in asm\tb1.asm
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-- Source for the 8080 program is in asm\tb1.asm
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-- Upon completion, a value of 055h in ACC means success and a 0aah means
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-- Upon completion, a value of 033h in ACC means success and a 0aah means
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-- failure, but the proper behavior of intr/inta/halt has to be verified
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-- failure, but the proper behavior of intr/inta/halt has to be verified
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-- visually.
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-- visually.
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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LIBRARY ieee;
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| Line 87... |
Line 87... |
X"01",X"c6",X"01",X"c6",X"01",X"fb",X"c6",X"01",
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X"01",X"c6",X"01",X"c6",X"01",X"fb",X"c6",X"01",
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X"c6",X"01",X"c6",X"01",X"fb",X"76",X"fe",X"11",
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X"c6",X"01",X"c6",X"01",X"fb",X"76",X"fe",X"11",
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X"c2",X"7b",X"00",X"78",X"fe",X"00",X"c2",X"7b",
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X"c2",X"7b",X"00",X"78",X"fe",X"00",X"c2",X"7b",
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X"00",X"79",X"fe",X"0c",X"c2",X"7b",X"00",X"7a",
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X"00",X"79",X"fe",X"0c",X"c2",X"7b",X"00",X"7a",
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X"fe",X"12",X"7b",X"fe",X"34",X"c2",X"7b",X"00",
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X"fe",X"12",X"7b",X"fe",X"34",X"c2",X"7b",X"00",
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X"3e",X"55",X"76",X"3e",X"aa",X"76",X"00",X"00",
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X"3e",X"33",X"76",X"3e",X"aa",X"76",X"00",X"00",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
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| Line 332... |
Line 332... |
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"
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);
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);
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type t_int_vectors is array(0 to 15) of std_logic_vector(7 downto 0);
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type t_int_vectors is array(0 to 15) of std_logic_vector(7 downto 0);
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-- This ROM holds the int vectors that will be fed to the CPU along the test.
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-- It will be read like a progrm ROM except a special pointer (vector_counter)
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-- will be used instead of the PC (see below).
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-- Of course this is a simulation trick not meant to be synthesized.
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signal int_vectors : t_int_vectors := (
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signal int_vectors : t_int_vectors := (
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X"00", -- not used
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X"00", -- not used (see below)
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X"e7", -- rst 4 (rst 20h)
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X"e7", -- rst 4 (rst 20h)
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X"4f", -- mov c,a
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X"4f", -- mov c,a
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X"11", X"34", X"12", -- lxi d, 1234h
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X"11", X"34", X"12", -- lxi d, 1234h
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X"00", -- nop
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X"00", -- nop
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X"00", -- not used
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X"00", -- not used
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X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00"
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X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00"
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);
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);
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-- This will be used to read the irq vector ROM. It's a pointer that increments
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-- whenever the CPU fetches a byte while inta_o is high.
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signal vector_counter : integer := 0;
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signal vector_counter : integer := 0;
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-- Vector byte to be fed to the CPU in inta cycles
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signal int_vector : std_logic_vector(7 downto 0);
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signal int_vector : std_logic_vector(7 downto 0);
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BEGIN
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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-- Instantiate the Unit Under Test (UUT)
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| Line 396... |
Line 402... |
wait for (sim_length - T*1.5);
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wait for (sim_length - T*1.5);
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-- Stop the clk process asserting 'done'
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-- Stop the clk process asserting 'done'
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done <= '1';
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done <= '1';
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assert (done = '1')
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assert (done = '1')
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report "Test finished."
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report "Test finished."
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severity failure;
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severity failure;
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wait;
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wait;
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end process main_test;
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end process main_test;
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-- RAM access
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-- (Code) RAM access
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process(clk)
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process(clk)
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begin
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begin
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if (clk'event and clk='1') then
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if (clk'event and clk='1') then
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data_mem <= rom(conv_integer(addr_o(10 downto 0)));
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data_mem <= rom(conv_integer(addr_o(10 downto 0)));
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if wr_o = '1' then
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if wr_o = '1' then
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rom(conv_integer(addr_o(10 downto 0))) <= data_o;
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rom(conv_integer(addr_o(10 downto 0))) <= data_o;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- Interrupt vector ROM pointer; update it whenever the CPU fetches a byte
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-- while in INTA state.
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process(clk)
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process(clk)
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begin
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begin
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if (clk'event and clk='1') then
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if (clk'event and clk='1') then
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if inta_o = '1' and vma_o = '1' and rd_o='1' then
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if inta_o = '1' and vma_o = '1' and rd_o='1' then
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vector_counter <= vector_counter + 1;
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vector_counter <= vector_counter + 1;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- (Since the vector pointer pre-increments and the ROM in asynchronous, the
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-- first byte of the ROM is never used).
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int_vector <= int_vectors(vector_counter);
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int_vector <= int_vectors(vector_counter);
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data_i <= data_mem when inta_o='0' else int_vector;
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data_i <= data_mem when inta_o='0' else int_vector;
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-- Trigger the IRQ input in a pattern carefully synchronized to the code of
|
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-- the test bench (see 'asm/tb1.asm').
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int0:
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int0:
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process
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process
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begin
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begin
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intr_i <= '0';
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intr_i <= '0';
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