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-- Light8080 simulation test bench.
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-- Light8080 simulation test bench.
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-- Source for the 8080 program is in asm\@PROGNAME@.asm
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-- This test bench was built from a generic template. The details on what tests
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-- are performed by this test bench can be found in the assembly source for the
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-- 8080 program, in file asm\@PROGNAME@.asm.
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--
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--
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-- This test bench provides a simulated CPU system to test programs. This test
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-- This test bench provides a simulated CPU system to test programs. This test
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-- bench does not do any assertions or checks, all assertions are left to the
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-- bench does not do any assertions or checks, all assertions are left to the
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-- software.
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-- software.
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-- Besides, it provides some means to trigger hardware irq from software,
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-- Besides, it provides some means to trigger hardware irq from software,
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-- including the specification of the instructions fed to the CPU as interrupt
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-- including the specification of the instructions fed to the CPU as interrupt
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-- vectors during inta cycles.
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-- vectors during inta cycles.
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--
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--
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-- We will simulate 8 possible irq sources. The software can trigger any one of
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-- We will simulate 8 possible irq sources. The software can trigger any one of
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-- them by writing at registers 0x010 and 0x011. Register 0x010 holds the irq
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-- them by writing at ports 0x010 to 0x011. Port 0x010 holds the irq source to
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-- source to be triggered (0 to 7) and register 0x011 holds the number of clock
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-- be triggered (0 to 7) and port 0x011 holds the number of clock cycles that
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-- cycles that will elapse from the end of the instruction that writes to the
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-- will elapse from the end of the instruction that writes to the register to
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-- register to the assertion of intr.
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-- the assertion of intr. Port 0x012 holds the number of cycles intr will remain
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-- high. Intr will be asserted for 1 cycle at least, so writing a 0 here is the
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-- same as writing 1.
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--
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--
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-- When the interrupt is acknowledged and inta is asserted, the test bench reads
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-- When the interrupt is acknowledged and inta is asserted, the test bench reads
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-- the value at register 0x010 as the irq source, and feeds an instruction to
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-- the value at register 0x010 as the irq source, and feeds an instruction to
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-- the CPU starting from the RAM address 0040h+source*4.
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-- the CPU starting from the RAM address 0040h+source*4.
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-- That is, address range 0040h-005fh is reserved for the simulated 'interrupt
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-- That is, address range 0040h-005fh is reserved for the simulated 'interrupt
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-- vectors', a total of 4 bytes for each of the 8 sources. This allows the
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-- vectors', a total of 4 bytes for each of the 8 sources. This allows the
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-- software to easily test different interrupt vectors without any hand
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-- software to easily test different interrupt vectors without any hand
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-- assembly. All of this is strictly simulation-only stuff.
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-- assembly. All of this is strictly simulation-only stuff.
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--
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--
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--
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-- Upon completion, the software must write a value to register 0x020. Writing
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-- Upon completion, the software must write a value to register 0x020. Writing
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-- a 0x055 means 'success', writing a 0x0aa means 'failure'. Success and
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-- a 0x055 means 'success', writing a 0x0aa means 'failure'. The write operation
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-- failure conditions are defined by the software.
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-- will stop the simulation. Success and failure conditions are defined by the
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-- software.
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--
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-- If a time period defined as constant MAX_SIM_LENGTH passes before anything
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-- is written to io address 0x020, the test bench assumes the software ran away
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-- and quits with an error message.
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library ieee;
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library ieee;
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use ieee.std_logic_1164.ALL;
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use ieee.std_logic_1164.ALL;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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);
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);
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signal irq_vector_byte: std_logic_vector(7 downto 0);
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signal irq_vector_byte: std_logic_vector(7 downto 0);
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signal irq_source : integer range 0 to 7;
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signal irq_source : integer range 0 to 7;
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signal cycles_to_intr : integer range -10 to 255;
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signal cycles_to_intr : integer range -10 to 255;
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signal intr_width : integer range 0 to 255;
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signal int_vector_index : integer range 0 to 3;
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signal int_vector_index : integer range 0 to 3;
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signal addr_vector_table: integer range 0 to 65535;
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signal addr_vector_table: integer range 0 to 65535;
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begin
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begin
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process(clk)
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process(clk)
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begin
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begin
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if (clk'event and clk='1') then
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if (clk'event and clk='1') then
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if reset='1' then
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if reset='1' then
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cycles_to_intr <= -10; -- meaning no interrupt pending
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cycles_to_intr <= -10; -- meaning no interrupt pending
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intr_i <= '0';
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else
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else
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if io_o='1' and wr_o='1' and addr_o(7 downto 0)=X"11" then
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if io_o='1' and wr_o='1' and addr_o(7 downto 0)=X"11" then
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cycles_to_intr <= conv_integer(data_o) + 1;
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cycles_to_intr <= conv_integer(data_o) + 1;
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else
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else
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if cycles_to_intr >= 0 then
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if cycles_to_intr >= 0 then
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cycles_to_intr <= cycles_to_intr - 1;
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cycles_to_intr <= cycles_to_intr - 1;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process irq_trigger_register;
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irq_pulse_width_register:
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process(clk)
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variable intr_pulse_countdown : integer;
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begin
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if (clk'event and clk='1') then
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if reset='1' then
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intr_width <= 1;
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intr_pulse_countdown := 0;
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intr_i <= '0';
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else
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if io_o='1' and wr_o='1' and addr_o(7 downto 0)=X"12" then
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intr_width <= conv_integer(data_o) + 1;
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end if;
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if cycles_to_intr = 0 then
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if cycles_to_intr = 0 then
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intr_i <= '1';
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intr_i <= '1';
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else
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intr_pulse_countdown := intr_width;
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elsif intr_pulse_countdown <= 1 then
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intr_i <= '0';
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intr_i <= '0';
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else
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intr_pulse_countdown := intr_pulse_countdown - 1;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process irq_pulse_width_register;
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end process irq_trigger_register;
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irq_source_register:
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irq_source_register:
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process(clk)
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process(clk)
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begin
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begin
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if (clk'event and clk='1') then
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if (clk'event and clk='1') then
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