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Line 27... |
│ │
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│ │
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│ └── rtl_sim RTL simulations
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│ └── rtl_sim RTL simulations
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│ ├── out Useful output from RTL simulation
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│ ├── out Useful output from RTL simulation
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│ └── run For running RTL simulations
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│ └── run For running RTL simulations
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│
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│
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└── sw Software sources for Python script utilities
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├── sw Software sources for Python script utilities
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├── out Useful output from Python script utilities
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│ ├── out Useful output from Python script utilities
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└── run Python sources and for running Python script utilities
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│ └── run Python sources and for running Python script utilities
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│
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└── uvm Universal Verification Methodology (UVM)
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├── work Work in progress/unfinished project
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│ └── generated_tb Test bench
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│
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└── tools Open-source Tools
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├── easier_uvm_gen Automatic UVM test bench generator
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└── uvm_syoscb General purpose UVM Scoreboard
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OPEN-SOURCE TOOLS:
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OPEN-SOURCE TOOLS:
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1. Ubuntu 18.04 LTS Linux OS development platform
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1. Ubuntu 18.04 LTS Linux OS development platform
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2. SystemC 2.3.2-Accellera SystemC test bench simulator
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2. SystemC 2.3.2-Accellera SystemC test bench simulator
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3. Verilator Verilog simulator
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3. Verilator Verilog simulator
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4. GTKWave Verilog simulation waveform viewer
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4. GTKWave Verilog simulation waveform viewer
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5. GNU Octave Octave syntax is largely compatible with MATLAB
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5. GNU Octave Octave syntax is largely compatible with MATLAB
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6. Python RTL-simulation vs. MATLAB-expected check script
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6. Python RTL-simulation vs. MATLAB-expected check script
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TO DO:
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1. Create Magnitude Response test of lpffir_core.sv with expected behavior of specification document Appendix B.
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2. Create Phase Response test of lpffir_core.sv with expected behavior of specification document Appendix B.
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