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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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// Verilog test bench
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// Verilog test bench
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module bench (
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module bench (
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input clk,
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input clk,
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input rst
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input rstn
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);
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);
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// Test case #1: check impulse response of low-pass filter.
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logic rx_tready;
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logic tx_tlast;
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logic tx_tvalid;
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logic [15:0] in = (count == 1) ? 1:0;
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logic [15:0] in = (count == 1) ? 1:0;
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logic [15:0] out;
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logic [15:0] out;
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reg [31:0] count;
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reg [31:0] count;
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always_ff @(posedge clk or posedge rst)
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always_ff @(posedge clk or posedge rstn)
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if (rst)
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if (!rstn)
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count <= 0;
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count <= 0;
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else
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else
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count <= count + 1;
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count <= count + 1;
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// unit under test(UUT)
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// unit under test(UUT)
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lpffir_core lpffir_core(.x_i(in),.clk_i(clk),.y_o(out));
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lpffir_axis lpffir_axis (
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.aclk_i(clk),
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.aresetn_i(rstn),
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.rx_tlast_i(0),
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.rx_tvalid_i(1),
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.rx_tready_o(rx_tready),
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.rx_tdate_i(in),
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.tx_tlast_o(tx_tlast),
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.tx_tvalid_o(tx_tvalid),
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.tx_tready_i(1),
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.tx_tdate_o(out)
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);
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// Test case log
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// Test case log
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initial begin
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initial begin
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$display("Test Case #1:");
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$display("Test Case #1:");
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$display("Check impulse response of low-pass filter.");
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$display("Check impulse response of low-pass filter.");
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$display("RTL simulation results:");
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$display("RTL simulation results:");
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$display("Input Output");
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$display("Input Output");
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$display("----- ------");
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$display("----- ------");
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end
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end
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always_ff @(posedge clk or posedge rst)
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always_ff @(posedge clk or posedge rstn)
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if(!rst)
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if(rstn)
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$display(" %0d %0d", in, out);
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$display(" %0d %0d", in, out);
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endmodule
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endmodule
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