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[/] [lq057q3dc02/] [trunk/] [design/] [components.vhd] - Diff between revs 30 and 38

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Rev 30 Rev 38
Line 16... Line 16... 
--  along with this program; if not, write to the Free Software
 
--  along with this program; if not, write to the Free Software
 
--  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 
--  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 
--
 
--
 
------------------------------------------------------------------------------
 
------------------------------------------------------------------------------
 
--
 
--
 
-- $Id: components.vhd,v 1.1 2008-11-07 00:48:12 jwdonal Exp $
 
-- $Id: components.vhd,v 1.2 2008-11-07 04:54:32 jwdonal Exp $
 
--
 
--
 
-- Description:
 
-- Description:
 
--   This is a package that lists all of the components used in the design.
 
--   This is a package that lists all of the components used in the design.
 
--
 
--
 
-- Structure:
 
-- Structure:
Line 72... Line 72... 
  -- DCM LCD Clock
 
  -- DCM LCD Clock
 
  ----------------------
 
  ----------------------
 
  COMPONENT dcm_sys_to_lcd
 
  COMPONENT dcm_sys_to_lcd
 
  PORT (
 
  PORT (
 
    RST_IN,
 
    RST_IN,
 
    CLKIN_IN : IN STD_LOGIC;
 
    CLKIN_IN : IN std_logic;
 
 
 
 
 
    CLKIN_IBUFG_OUT,
 
    CLKIN_IBUFG_OUT,
 
    CLK0_OUT,
 
    CLK0_OUT,
 
    CLKDV_OUT,
 
    CLKDV_OUT,
 
    CLKFX_OUT       : OUT STD_LOGIC
 
    CLKFX_OUT       : OUT std_logic
 
  );
 
  );
 
  END COMPONENT dcm_sys_to_lcd;
 
  END COMPONENT dcm_sys_to_lcd;
 
 
 
 
 
 
 
 
 
  ----------------------
 
  ----------------------
Line 117... Line 117... 
  COMPONENT video_controller is
 
  COMPONENT video_controller is
 
  GENERIC (
 
  GENERIC (
 
    --Video Controller
 
    --Video Controller
 
    C_RL_STATUS,
 
    C_RL_STATUS,
 
    C_UD_STATUS,
 
    C_UD_STATUS,
 
    C_VQ_STATUS : STD_LOGIC;
 
    C_VQ_STATUS : std_logic;
 
 
 
 
 
    --VSYNCx Controller (pass thru)
 
    --VSYNCx Controller (pass thru)
 
    C_VSYNC_TV,
 
    C_VSYNC_TV,
 
    C_VSYNC_TVP,
 
    C_VSYNC_TVP,
 
    C_VSYNC_TVS,
 
    C_VSYNC_TVS,
Line 140... Line 140... 
    C_ENAB_THE : POSITIVE
 
    C_ENAB_THE : POSITIVE
 
  );
 
  );
 
 
 
 
 
  PORT (
 
  PORT (
 
    RSTx,
 
    RSTx,
 
    CLK_LCD : IN  STD_LOGIC;
 
    CLK_LCD : IN  std_logic;
 
 
 
 
 
    LINE_NUM : OUT STD_LOGIC_VECTOR(C_LINE_NUM_WIDTH-1 downto 0);
 
    LINE_NUM : OUT std_logic_VECTOR(C_LINE_NUM_WIDTH-1 downto 0);
 
 
 
 
 
    CLK_LCD_CYC_NUM : OUT STD_LOGIC_VECTOR(C_CLK_LCD_CYC_NUM_WIDTH-1 downto 0);
 
    CLK_LCD_CYC_NUM : OUT std_logic_VECTOR(C_CLK_LCD_CYC_NUM_WIDTH-1 downto 0);
 
 
 
 
 
    HSYNCx,
 
    HSYNCx,
 
    VSYNCx,
 
    VSYNCx,
 
    ENAB,
 
    ENAB,
 
    RL,
 
    RL,
 
    UD,
 
    UD,
 
    VQ    : OUT STD_LOGIC
 
    VQ    : OUT std_logic
 
  );
 
  );
 
  END COMPONENT video_controller;
 
  END COMPONENT video_controller;
 
 
 
 
 
 
 
 
 
  ----------------------
 
  ----------------------
Line 167... Line 167... 
    C_HSYNC_THP,
 
    C_HSYNC_THP,
 
    C_NUM_CLKS_WIDTH : POSITIVE
 
    C_NUM_CLKS_WIDTH : POSITIVE
 
  );
 
  );
 
  PORT (
 
  PORT (
 
    RSTx,
 
    RSTx,
 
    CLK_LCD : IN  STD_LOGIC;
 
    CLK_LCD : IN  std_logic;
 
 
 
 
 
    HSYNCx  : OUT STD_LOGIC
 
    HSYNCx  : OUT std_logic
 
  );
 
  );
 
  END COMPONENT hsyncx_control;
 
  END COMPONENT hsyncx_control;
 
 
 
 
 
 
 
 
 
  ----------------------
 
  ----------------------
Line 187... Line 187... 
  );
 
  );
 
 
 
 
 
  PORT (
 
  PORT (
 
    RSTx,
 
    RSTx,
 
    CLK_LCD,
 
    CLK_LCD,
 
    HSYNCx   : IN  STD_LOGIC;
 
    HSYNCx   : IN  std_logic;
 
 
 
 
 
    LINE_NUM : OUT STD_LOGIC_VECTOR(C_LINE_NUM_WIDTH-1 downto 0);
 
    LINE_NUM : OUT std_logic_VECTOR(C_LINE_NUM_WIDTH-1 downto 0);
 
 
 
 
 
    VSYNCx   : OUT STD_LOGIC
 
    VSYNCx   : OUT std_logic
 
  );
 
  );
 
  END COMPONENT vsyncx_control;
 
  END COMPONENT vsyncx_control;
 
 
 
 
 
 
 
 
 
  ----------------------
 
  ----------------------
Line 210... Line 210... 
    C_ENAB_TEP,
 
    C_ENAB_TEP,
 
    C_ENAB_THE : POSITIVE
 
    C_ENAB_THE : POSITIVE
 
  );
 
  );
 
  PORT (
 
  PORT (
 
    RSTx,
 
    RSTx,
 
    CLK_LCD : IN STD_LOGIC;
 
    CLK_LCD : IN std_logic;
 
 
 
 
 
    CLK_LCD_CYC_NUM : IN STD_LOGIC_VECTOR(C_CLK_LCD_CYC_NUM_WIDTH-1 downto 0);
 
    CLK_LCD_CYC_NUM : IN std_logic_VECTOR(C_CLK_LCD_CYC_NUM_WIDTH-1 downto 0);
 
 
 
 
 
    ENAB  : OUT STD_LOGIC
 
    ENAB  : OUT std_logic
 
  );
 
  );
 
  END COMPONENT enab_control;
 
  END COMPONENT enab_control;
 
 
 
 
 
 
 
 
 
  -----------------------
 
  -----------------------
Line 240... Line 240... 
    C_IMAGE_WIDTH,
 
    C_IMAGE_WIDTH,
 
    C_IMAGE_HEIGHT : POSITIVE
 
    C_IMAGE_HEIGHT : POSITIVE
 
  );
 
  );
 
  PORT (
 
  PORT (
 
    RSTx,
 
    RSTx,
 
    CLK_LCD : IN STD_LOGIC;
 
    CLK_LCD : IN std_logic;
 
 
 
 
 
    LINE_NUM : IN STD_LOGIC_VECTOR(C_LINE_NUM_WIDTH-1 downto 0);
 
    LINE_NUM : IN std_logic_VECTOR(C_LINE_NUM_WIDTH-1 downto 0);
 
 
 
 
 
    CLK_LCD_CYC_NUM : IN STD_LOGIC_VECTOR(C_CLK_LCD_CYC_NUM_WIDTH-1 downto 0);
 
    CLK_LCD_CYC_NUM : IN std_logic_VECTOR(C_CLK_LCD_CYC_NUM_WIDTH-1 downto 0);
 
 
 
 
 
    R,
 
    R,
 
    G,
 
    G,
 
    B : OUT STD_LOGIC_VECTOR(C_BIT_DEPTH/3-1 downto 0)
 
    B : OUT std_logic_VECTOR(C_BIT_DEPTH/3-1 downto 0)
 
  );
 
  );
 
  END COMPONENT image_gen_bram;
 
  END COMPONENT image_gen_bram;
 
 
 
 
 
 
 
 
 
  --------------------------
 
  --------------------------
Line 265... Line 265... 
  --resets the output back to '0' whenever it is disabled.  Which is exactly what we want
 
  --resets the output back to '0' whenever it is disabled.  Which is exactly what we want
 
  --b/c if the last value reamins (as it would with EN) the last pixel drawn for the
 
  --b/c if the last value reamins (as it would with EN) the last pixel drawn for the
 
  --image in each row would be "smeared" across the remaining pixels in the row!
 
  --image in each row would be "smeared" across the remaining pixels in the row!
 
  COMPONENT image_gen_bram_red
 
  COMPONENT image_gen_bram_red
 
  PORT (
 
  PORT (
 
    CLK,
 
    clka : IN std_logic;
 
    SINIT : IN STD_LOGIC;
 
    addra : IN std_logic_VECTOR(17-1 downto 0);
 
    ADDR : IN STD_LOGIC_VECTOR(17-1 downto 0);
 
    douta : OUT std_logic_VECTOR(6-1 downto 0)
 
    DOUT : OUT STD_LOGIC_VECTOR(6-1 downto 0)
 
 
 
  );
 
  );
 
  END COMPONENT;
 
  END COMPONENT;
 
  ATTRIBUTE BOX_TYPE of image_gen_bram_red: component is "USER_BLACK_BOX";
 
  ATTRIBUTE BOX_TYPE of image_gen_bram_red: component is "USER_BLACK_BOX";
 
 
 
 
 
  COMPONENT image_gen_bram_green
 
  COMPONENT image_gen_bram_green
 
  PORT (
 
  PORT (
 
    CLK,
 
    clka : IN std_logic;
 
    SINIT : IN STD_LOGIC;
 
    addra : IN std_logic_VECTOR(17-1 downto 0);
 
    ADDR : IN STD_LOGIC_VECTOR(17-1 downto 0);
 
    douta : OUT std_logic_VECTOR(6-1 downto 0)
 
    DOUT : OUT STD_LOGIC_VECTOR(6-1 downto 0)
 
 
 
  );
 
  );
 
  END COMPONENT;
 
  END COMPONENT;
 
  ATTRIBUTE BOX_TYPE of image_gen_bram_green: component is "USER_BLACK_BOX";
 
  ATTRIBUTE BOX_TYPE of image_gen_bram_green: component is "USER_BLACK_BOX";
 
 
 
 
 
  COMPONENT image_gen_bram_blue
 
  COMPONENT image_gen_bram_blue
 
  PORT (
 
  PORT (
 
    CLK,
 
    clka : IN std_logic;
 
    SINIT : IN STD_LOGIC;
 
    addra : IN std_logic_VECTOR(17-1 downto 0);
 
    ADDR : IN STD_LOGIC_VECTOR(17-1 downto 0);
 
    douta : OUT std_logic_VECTOR(6-1 downto 0)
 
    DOUT : OUT STD_LOGIC_VECTOR(6-1 downto 0)
 
 
 
  );
 
  );
 
  END COMPONENT;
 
  END COMPONENT;
 
  ATTRIBUTE BOX_TYPE of image_gen_bram_blue: component is "USER_BLACK_BOX";
 
  ATTRIBUTE BOX_TYPE of image_gen_bram_blue: component is "USER_BLACK_BOX";
 
 
 
 
 
 
 
 

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