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Release 9.2.04i par J.40
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Release 9.2.04i par J.40
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Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
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Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
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NAUTILUS:: Thu Nov 06 18:46:08 2008
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NAUTILUS:: Sun Nov 09 22:14:10 2008
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par -ol high -w lq057q3dc02_top.ncd lq057q3dc02_top.ncd lq057q3dc02_top.pcf
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par -ol high -w lq057q3dc02_top.ncd lq057q3dc02_top.ncd lq057q3dc02_top.pcf
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Constraints file: lq057q3dc02_top.pcf.
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Constraints file: lq057q3dc02_top.pcf.
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Starting initial Timing Analysis. REAL time: 9 secs
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Starting initial Timing Analysis. REAL time: 9 secs
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Finished initial Timing Analysis. REAL time: 9 secs
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Finished initial Timing Analysis. REAL time: 9 secs
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Starting Router
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Starting Router
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Phase 1: 4052 unrouted; REAL time: 21 secs
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Phase 1: 4052 unrouted; REAL time: 20 secs
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Phase 2: 3381 unrouted; REAL time: 22 secs
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Phase 2: 3381 unrouted; REAL time: 21 secs
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Phase 3: 340 unrouted; REAL time: 26 secs
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Phase 3: 340 unrouted; REAL time: 25 secs
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Phase 4: 340 unrouted; (0) REAL time: 26 secs
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Phase 4: 340 unrouted; (0) REAL time: 25 secs
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Phase 5: 340 unrouted; (0) REAL time: 26 secs
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Phase 5: 340 unrouted; (0) REAL time: 25 secs
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Phase 6: 340 unrouted; (0) REAL time: 26 secs
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Phase 6: 340 unrouted; (0) REAL time: 25 secs
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Phase 7: 0 unrouted; (0) REAL time: 27 secs
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Phase 7: 0 unrouted; (0) REAL time: 26 secs
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Phase 8: 0 unrouted; (0) REAL time: 28 secs
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Phase 8: 0 unrouted; (0) REAL time: 27 secs
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WARNING:Route:455 - CLK Net:CLK_LCD_OBUF may have excessive skew because
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WARNING:Route:455 - CLK Net:CLK_LCD_OBUF may have excessive skew because
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0 CLK pins and 1 NON_CLK pins failed to route using a CLK template.
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0 CLK pins and 1 NON_CLK pins failed to route using a CLK template.
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Total REAL time to Router completion: 28 secs
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Total REAL time to Router completion: 27 secs
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Total CPU time to Router completion: 28 secs
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Total CPU time to Router completion: 27 secs
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Partition Implementation Status
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Partition Implementation Status
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-------------------------------
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-------------------------------
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No Partitions were found in this design.
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No Partitions were found in this design.
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Line 129... |
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Generating Pad Report.
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Generating Pad Report.
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All signals are completely routed.
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All signals are completely routed.
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Total REAL time to PAR completion: 31 secs
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Total REAL time to PAR completion: 29 secs
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Total CPU time to PAR completion: 30 secs
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Total CPU time to PAR completion: 28 secs
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Peak Memory Usage: 201 MB
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Peak Memory Usage: 201 MB
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Placer: Placement generated during map.
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Placer: Placement generated during map.
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Routing: Completed - No errors found.
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Routing: Completed - No errors found.
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