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/******************************************************************
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* *
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* Author: Liwei *
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* *
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* This file is part of the "ClaiRISC" project, *
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* The folder in CVS is named as "lwrisc" *
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* Downloaded from: *
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* http://www.opencores.org/pdownloads.cgi/list/lwrisc *
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* *
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* If you encountered any problem, please contact me via *
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* Email:mcupro@opencores.org or mcupro@163.com *
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* *
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******************************************************************/
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`include "clairisc_def.h"
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`include "clairisc_def.h"
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`define ADDR_FSR 4
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`define ADDR_STATUS 3
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`define ADDR_STATUS 3
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`define ADDR_IN0 5
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`define ADDR_DVC_DATA 0
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`define ADDR_IN1 1
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`define ADDR_DVC_WR_ADDR 2
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`define ADDR_OUT0 6
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`define ADDR_DVC_RD_ADDR 1
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`define ADDR_OUT1 7
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/*
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#define PORT_DATA *(unsigned char*)0
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#define IN_PORT_ADDR *(unsigned char*)1
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#define OUT_PORT_ADDR *(unsigned char*)2
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#define STATUS *(unsigned char*)3
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*/
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module wb_mem_man(
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module mem_man(
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input wr_en,
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input wr_en,
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input clk,
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input clk,
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input rst,
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input rst,
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input ci,
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input ci,
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input zi,
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input zi,
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input z_wr,
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input z_wr,
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input c_wr,
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input c_wr,
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output reg [7:0] dout,
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output reg [7:0] dout,
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output co,
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output co,
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output [1:0] bank,
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input [7:0] din ,
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input [7:0] din ,
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output reg [7:0]status ,
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output reg [7:0]status ,
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input [7:0] rd_addr, //[6:0]Should be also OK,For there is only 128byte RAM
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input [4:0] rd_addr,
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input [7:0] wr_addr , //[6:0]Should be also OK,For there is only 128byte RAM
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input [4:0] wr_addr ,
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input [7:0] in0,
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output reg [7:0]dvc_wr_addr,
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input [7:0] in1,
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output reg [7:0]dvc_rd_addr,
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output reg [7:0] out0,
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output reg [7:0]data_mem2dvc,
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output reg [7:0] out1
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input [7:0]data_dvc2mem,
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output reg dvc_wr ,
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output /*reg */dvc_rd
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);
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);
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reg wr_en_r;
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reg wr_en_r;
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reg [7:0] din_r, wr_addr_r;
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reg [7:0] din_r;
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reg [7:0] rd_addr_r;
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reg [4:0] wr_addr_r;
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reg [4:0] rd_addr_r;
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always @(posedge clk)
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always @(posedge clk)
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begin //used to bypass the data
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begin
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//which wrote anf then be read in the followwing period
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wr_addr_r<=wr_addr;
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wr_addr_r<=wr_addr;
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rd_addr_r<=rd_addr;
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rd_addr_r<=rd_addr;
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wr_en_r<=wr_en;
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wr_en_r<=wr_en;
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din_r<=din;
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din_r<=din;
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end
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end
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wire [7:0] ram_q ;
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wire [7:0] ram_q ;
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wire [7:0] alt_ram_q;
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wire [7:0] alt_ram_q;
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`ifdef SIM
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// `ifdef SIM
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sim_reg_file i_reg_file(
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sim_reg_file i_reg_file(
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.data(din),
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.data(din),
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.wren(wr_en),
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.wren(wr_en),
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.wraddress(wr_addr),
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.wraddress(wr_addr[4:0]),
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.rdaddress(rd_addr),
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.rdaddress(rd_addr[4:0]),
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.clock(clk),
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.clock(clk),
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.q(alt_ram_q));
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.q(alt_ram_q));
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`else
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/* `else
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ram128x8 i_reg_file(
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ram128x8 i_reg_file(
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.data(din),
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.data(din),
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.wren(wr_en),
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.wren(wr_en),
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.wraddress(wr_addr),
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.wraddress(wr_addr),
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.rdaddress(rd_addr),
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.rdaddress(rd_addr),
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.clock(clk),
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.clock(clk),
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.q(alt_ram_q)
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.q(alt_ram_q)
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);
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);
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`endif
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`endif
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*/
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assign ram_q = ((wr_addr_r==rd_addr_r)&&(wr_en_r))?din_r:alt_ram_q;
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assign ram_q =/* ((wr_addr_r==rd_addr_r)&&(wr_en_r))?din_r:*/alt_ram_q;
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/*status register*/
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/*status register*/
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wire write_status = wr_addr[4:0] ==`ADDR_STATUS && wr_en;
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wire write_status = wr_addr[4:0] ==`ADDR_STATUS && wr_en;
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always@(posedge clk)
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always@(posedge clk)
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begin
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begin
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end
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end
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assign co = status[0];
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assign co = status[0];
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`ifdef SIM
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`ifdef SIM
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always@(*)
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wire write_disp = wr_addr == 'h1f && wr_en;
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always@(posedge clk)
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begin
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begin
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if (write_disp)
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if (wr_en)
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$display("hex=>%x< char=>%c<",din,din);
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$display("hex=>%x< char=>%x<",wr_addr[4:0],din[7:0]);
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end
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end
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`endif
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`endif
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/*fsr register*/
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always@(*)
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reg [7:0] fsr;
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assign bank = fsr[6:5];
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wire write_fsr = wr_addr[4:0] == `ADDR_FSR &&wr_en ;
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always@(posedge clk)
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begin
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if (rst)fsr<=0;
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else if(write_fsr) fsr<=din[7:0];
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end
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/*latch the input data*/
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reg [7:0] reg_in1,reg_in0;
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always@(posedge clk) reg_in0<=in0;
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always@(posedge clk) reg_in1<=in1;
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/*data output latch */
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wire write_out0 = wr_addr[4:0] == `ADDR_OUT0 &&wr_en ;
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always@(posedge clk)
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begin
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if (rst)out0<=0;
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else if(write_out0)out0<=din[7:0];
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end
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/*data output latch */
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wire write_out1 = wr_addr[4:0] == `ADDR_OUT1 &&wr_en ;
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always@(posedge clk)
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begin
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if (rst)out1<=0;
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else if(write_out1)out1<=din[7:0];
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end
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/*data bus output select logic*/
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always@(*)//select status,fsr,wb_data,ram,wb_din
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case(rd_addr_r[4:0])
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case(rd_addr_r[4:0])
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`ADDR_FSR:dout = fsr;
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`ADDR_STATUS:dout = status;
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`ADDR_STATUS:dout = status;
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`ADDR_IN0:dout = reg_in0;
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`ADDR_DVC_DATA :dout = data_dvc2mem ;
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`ADDR_IN1:dout = reg_in1;
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default dout = ram_q ;
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default dout = ram_q ;
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endcase
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endcase
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always @ (posedge clk) if ((wr_addr[4:0]==`ADDR_DVC_WR_ADDR)&&(1==wr_en))dvc_wr_addr <=din;
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always @ (posedge clk) if ((wr_addr[4:0]==`ADDR_DVC_RD_ADDR)&&(1==wr_en)) dvc_rd_addr <=din;
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always @ (posedge clk) if ((wr_addr[4:0]==`ADDR_DVC_DATA )&&(1==wr_en)) data_mem2dvc <=din;
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always @ (*) dvc_wr <=wr_en_r&(wr_addr==0);
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assign dvc_rd = 1'b1 ;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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