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Line 1... Line 1... 
/******************************************************************
 
 
 
 *                                                                *
 
 
 
 *    Author: Liwei                                               *
 
 
 
 *                                                                *
 
 
 
 *    This file is part of the "ClaiRISC" project,                *
 
 
 
 *    The folder in CVS is named as "lwrisc"                      *
 
 
 
 *    Downloaded from:                                            *
 
 
 
 *    http://www.opencores.org/pdownloads.cgi/list/lwrisc         *
 
 
 
 *                                                                *
 
 
 
 *    If you encountered any problem, please contact me via       *
 
 
 
 *    Email:mcupro@opencores.org  or mcupro@163.com               *
 
 
 
 *                                                                *
 
 
 
 ******************************************************************/
 
 
 
 
 
 
 
`include "clairisc_def.h"
 
`include "clairisc_def.h"
 
module ClaiRISC_core (
 
module ClaiRISC_core (
 
        input clk,
 
        input clk,
 
        input rst               ,
 
        input rst               ,
 
        input [7:0] in0,
 
        output [7:0]dvc_wr_addr,
 
        input [7:0] in1,
 
        output [7:0]dvc_rd_addr,
 
        output [7:0] out0,
 
        output  [7:0]data_mem2dvc,
 
        output [7:0] out1
 
        input [7:0]data_dvc2mem,
 
 
 
        output dvc_wr  ,
 
 
 
        output dvc_rd
 
    );
 
    );
 
 
 
 
 
    supply0 GND;
 
    supply0 GND;
 
    wire w_c_2alu;
 
    wire w_c_2alu;
 
    wire w_c_2mem;
 
    wire w_c_2mem;
Line 52... Line 41... 
    wire [7:0] w_file_o;
 
    wire [7:0] w_file_o;
 
    wire [11:0] w_ins;
 
    wire [11:0] w_ins;
 
    reg [10:0] w_pc;
 
    reg [10:0] w_pc;
 
    reg [2:0] w_pc_gen_ctl;
 
    reg [2:0] w_pc_gen_ctl;
 
    reg [10:0] w_pc_nxt;
 
    reg [10:0] w_pc_nxt;
 
    wire [6:0] w_rd_addr;
 
    wire [4:0] w_rd_addr;
 
    wire [7:0] w_status;
 
    wire [7:0] w_status;
 
    reg [1:0] w_stk_op;
 
    reg [1:0] w_stk_op;
 
    wire [10:0] w_stk_pc;
 
    wire [10:0] w_stk_pc;
 
    reg[4:0] w_wbadd_r;
 
    reg[4:0] w_wbadd_r;
 
    wire [4:0] w_wd_addr;
 
    wire [4:0] w_wd_addr;
 
    reg [7:0] w_wreg;
 
    reg [7:0] w_wreg;
 
    wire [6:0] w_wr_addr;
 
    wire [4:0] w_wr_addr;
 
 
 
 
 
    always @(posedge clk)
 
    always @(posedge clk)
 
        w_pc<=w_pc_nxt;
 
        w_pc<=w_pc_nxt;
 
 
 
 
 
    reg [10:0]   stack1, stack2, stack3, stack4;
 
    reg [10:0]   stack1, stack2, stack3, stack4;
 
 
 
 
 
 
 
        initial begin
 
 
 
        stack1=0;
 
 
 
        stack2=0;
 
 
 
        stack3=0;
 
 
 
        stack4=0;
 
 
 
        end
 
 
 
 
 
    assign w_stk_pc = stack1;
 
    assign w_stk_pc = stack1;
 
 
 
 
 
    always @(posedge clk)
 
    always @(posedge clk)
 
    begin
 
    begin
 
        case (w_stk_op)
 
        case (w_stk_op)
 
            `STK_PSH    :// PUSH stack
 
            `STK_PSH    :// PUSH stack
 
            begin
 
            begin
 
                stack4 <= stack3;
 
                stack4 <= stack3;
 
                stack3 <= stack2;
 
                stack3 <= stack2;
 
                stack2 <= stack1;
 
                stack2 <= stack1;
 
                stack1 <= w_pc;
 
                stack1 <= w_pc+1;
 
            end
 
            end
 
            `STK_POP    :// POP stack
 
            `STK_POP    :// POP stack
 
            begin
 
            begin
 
                stack1 <= stack2;
 
                stack1 <= stack2;
 
                stack2 <= stack3;
 
                stack2 <= stack3;
Line 87... Line 84... 
            end
 
            end
 
            //  default ://do nothing
 
            //  default ://do nothing
 
        endcase
 
        endcase
 
    end
 
    end
 
 
 
 
 
    assign         w_rd_addr ={ w_bank[1:0],w_wd_addr[4:0]};
 
    assign         w_rd_addr =w_wd_addr[4:0];
 
 
 
 
 
    wb_mem_man   mem_man
 
    mem_man   mem_man
 
                 (
 
                 (
 
                     .bank(w_bank),
 
 
 
                     .c_wr(w_c_wr_r),
 
                     .c_wr(w_c_wr_r),
 
                     .ci(w_c_2mem),
 
                     .ci(w_c_2mem),
 
                     .clk(clk),
 
                     .clk(clk),
 
                     .co(w_c_2alu),
 
                     .co(w_c_2alu),
 
                     .din(w_alu_res),
 
                     .din(w_alu_res),
 
                     .dout(w_file_o),
 
                     .dout(w_file_o),
 
                     .rd_addr(w_rd_addr),
 
                     .rd_addr(w_rd_addr[4:0]),
 
                     .rst(rst),
 
                     .rst(rst),
 
                     .status(w_status),
 
                     .status(w_status),
 
                     .wr_addr(w_wr_addr),
 
                     .wr_addr(w_wr_addr[4:0]),
 
                     .wr_en(w_mem_wr_r),
 
                     .wr_en(w_mem_wr_r),
 
                     .z_wr(w_z_wr_r),
 
                     .z_wr(w_z_wr_r),
 
                     .zi(w_z),
 
                     .zi(w_z),
 
                     .in0(in0),
 
                                         .dvc_wr_addr(dvc_wr_addr),
 
                     .in1(in1),
 
                         .dvc_rd_addr(dvc_rd_addr),
 
                     .out0(out0),
 
                         .data_mem2dvc(data_mem2dvc),
 
                     .out1(out1)
 
                         .data_dvc2mem(data_dvc2mem),
 
 
 
                         .dvc_wr(dvc_wr),
 
 
 
                                         .dvc_rd(dvc_rd)
 
                 );
 
                 );
 
 
 
 
 
    always @(posedge clk)
 
    always @(posedge clk)
 
        if (w_skip==1)
 
        if (w_skip)
 
            w_alu_op_r<=0;
 
            w_alu_op_r<=0;
 
        else
 
        else
 
            w_alu_op_r<=w_alu_op;
 
            w_alu_op_r<=w_alu_op;
 
 
 
 
 
    always@(posedge clk)
 
    always@(posedge clk)
 
        if (w_skip==1)    w_br_ctl_r<=0;
 
        if (w_skip)       w_br_ctl_r<=0;
 
        else w_br_ctl_r<=w_brc_ctl;
 
        else w_br_ctl_r<=w_brc_ctl;
 
 
 
 
 
    always@(posedge clk)
 
    always@(posedge clk)
 
        if (w_skip==1)    w_z_wr_r<=0;
 
        if (w_skip)       w_z_wr_r<=0;
 
        else  w_z_wr_r<=w_z_wr;
 
        else  w_z_wr_r<=w_z_wr;
 
 
 
 
 
    always @ (posedge clk)
 
    always @ (posedge clk)
 
        if (w_skip==1)
 
        if (w_skip)
 
            w_c_wr_r<=0;
 
            w_c_wr_r<=0;
 
        else
 
        else
 
            w_c_wr_r<=w_c_wr;
 
            w_c_wr_r<=w_c_wr;
 
 
 
 
 
    always @(posedge clk)
 
    always @(posedge clk)
 
        if(w_skip==1)
 
        if(w_skip)
 
            w_mem_wr_r<=0;
 
            w_mem_wr_r<=0;
 
        else
 
        else
 
            w_mem_wr_r<=w_mem_wr;
 
            w_mem_wr_r<=w_mem_wr;
 
 
 
 
 
    always @(posedge clk)
 
    always @(posedge clk)
 
        if (w_w_wr_r==1)
 
        if (w_w_wr_r)
 
            w_wreg<=w_alu_res;
 
            w_wreg<=w_alu_res;
 
 
 
 
 
        always @ (posedge clk)
 
        always @ (posedge clk)
 
                w_bd_r<=1<<w_ins[7:5];
 
                w_bd_r<=1<<w_ins[7:5];
 
 
 
 
Line 155... Line 153... 
    assign w_wd_addr = w_ins[4:0];
 
    assign w_wd_addr = w_ins[4:0];
 
 
 
 
 
    always@(posedge clk)
 
    always@(posedge clk)
 
        w_wbadd_r<=w_wd_addr;
 
        w_wbadd_r<=w_wd_addr;
 
 
 
 
 
    assign w_wr_addr = {w_bank[1:0],w_wbadd_r[4:0]};
 
 
 
 
 
 
 
 
 
 
 
 
 
           assign w_wr_addr =  w_wbadd_r[4:0];
 
    reg         addercout;
 
    reg         addercout;
 
    always @(*) begin
 
    always @(*) begin
 
        case (w_alu_op_r) // synsys parallel_case
 
        case (w_alu_op_r) // synsys parallel_case
 
            `ALU_ADD:   {addercout,  w_alu_res}  = w_alu_in_a + w_alu_in_b;
 
            `ALU_ADD:   {addercout,  w_alu_res}  = w_alu_in_a + w_alu_in_b;
 
            `ALU_SUB:  {addercout,  w_alu_res}  = w_alu_in_b - w_alu_in_a;
 
            `ALU_SUB:  {addercout,  w_alu_res}  = w_alu_in_b - w_alu_in_a;
Line 217... Line 214... 
        `BG_NZERO :w_skip = (w_z==0);     //if the ALU result is not zero
 
        `BG_NZERO :w_skip = (w_z==0);     //if the ALU result is not zero
 
        //then skip the next instruction
 
        //then skip the next instruction
 
        default w_skip = 0;
 
        default w_skip = 0;
 
    endcase
 
    endcase
 
 
 
 
 
 
 
com_prom program_rom
 
    pram program_rom
 
 
 
         (
 
         (
 
             .clk(clk),
 
             .clk(clk),
 
             .dout(w_ins),
 
             .dout(w_ins),
 
             .rd_addr(w_pc_nxt)
 
             .rd_addr(w_pc_nxt)
 
         );
 
         );
Line 237... Line 233... 
            end
 
            end
 
            else
 
            else
 
            begin
 
            begin
 
                case(w_pc_gen_ctl)
 
                case(w_pc_gen_ctl)
 
                    `PC_GOTO,
 
                    `PC_GOTO,
 
                    `PC_CALL:    w_pc_nxt= {w_status[7:6],w_ins[8:0]};
 
                    `PC_CALL:   w_pc_nxt= w_ins[7:0];//{w_status[7:6],1'b0,w_ins[7:0]};
 
                    `PC_RET:    w_pc_nxt= w_stk_pc;
 
                    `PC_RET:    w_pc_nxt= w_stk_pc;
 
                    default
 
                    default
 
                    w_pc_nxt= w_pc+1;
 
                    w_pc_nxt= w_pc+1;
 
                endcase
 
                endcase
 
            end
 
            end
Line 820... Line 816... 
 
 
 
 
            12'b1000_XXXX_XXXX:
 
            12'b1000_XXXX_XXXX:
 
                //REPLACE ID = RETLW
 
                //REPLACE ID = RETLW
 
                //REPLACE ID = RETLW
 
                //REPLACE ID = RETLW
 
            begin
 
            begin
 
                w_pc_gen_ctl = `PC_NEXT;
 
                w_pc_gen_ctl = `PC_RET ;
 
                w_stk_op = `STK_POP;
 
                w_stk_op = `STK_POP;
 
                w_muxa_ctl = `MUXA_IGN;
 
                w_muxa_ctl = `MUXA_IGN;
 
                w_muxb_ctl = `MUXB_EK;                     //check 2008_11_22
 
                w_muxb_ctl = `MUXB_EK;                     //check 2008_11_22
 
                w_alu_op = `ALU_PB;
 
                w_alu_op = `ALU_PB;
 
                w_mem_wr = `DIS;
 
                w_mem_wr = `DIS;
Line 945... Line 941... 
                w_c_wr = `DIS;
 
                w_c_wr = `DIS;
 
                w_brc_ctl = `BG_NOP;
 
                w_brc_ctl = `BG_NOP;
 
            end //end of NOP ;
 
            end //end of NOP ;
 
        endcase
 
        endcase
 
    end
 
    end
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 
 
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