| Line 26... |
Line 26... |
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interrupt_valid_i: in std_logic;
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interrupt_valid_i: in std_logic;
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interrupt_vector_i: in std_logic_vector(2 downto 0);
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interrupt_vector_i: in std_logic_vector(2 downto 0);
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interrupt_ready_o: out std_logic;
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interrupt_ready_o: out std_logic;
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wakeup_i: in std_logic;
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sp_raddr1_o: out std_logic_vector(7 downto 0);
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sp_raddr1_o: out std_logic_vector(7 downto 0);
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sp_rdata1_i: in std_logic_vector(31 downto 0);
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sp_rdata1_i: in std_logic_vector(31 downto 0);
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sp_raddr2_o: out std_logic_vector(7 downto 0);
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sp_raddr2_o: out std_logic_vector(7 downto 0);
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sp_rdata2_i: in std_logic_vector(31 downto 0);
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sp_rdata2_i: in std_logic_vector(31 downto 0);
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Line 100... |
signal rd2_direct: std_logic_vector(31 downto 0);
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signal rd2_direct: std_logic_vector(31 downto 0);
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-- Signals related to interrupt handling
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-- Signals related to interrupt handling
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signal interrupt_ready: std_logic:='0';
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signal interrupt_ready: std_logic:='0';
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signal wakeup_reg: std_logic:='0';
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begin
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begin
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-- Dissect input word
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-- Dissect input word
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Line 149... |
rd2_select<='-';
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rd2_select<='-';
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rd2_direct<=(others=>'-');
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rd2_direct<=(others=>'-');
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op3_o<=(others=>'-');
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op3_o<=(others=>'-');
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jump_type_o<=(others=>'-');
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jump_type_o<=(others=>'-');
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dst_out<=(others=>'-');
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dst_out<=(others=>'-');
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wakeup_reg<='0';
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else
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else
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interrupt_ready<='0';
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interrupt_ready<='0';
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wakeup_reg<=wakeup_reg or wakeup_i;
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if jump_valid_i='1' then
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if jump_valid_i='1' then
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valid_out<='0';
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valid_out<='0';
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self_busy<='0';
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self_busy<='0';
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state<=Regular;
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state<=Regular;
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elsif downstream_busy='0' then
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elsif downstream_busy='0' then
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| Line 255... |
Line 260... |
self_busy<='0';
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self_busy<='0';
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state<=ContinueLc;
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state<=ContinueLc;
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elsif opcode="000010" then
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elsif opcode="000010" then
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valid_out<='0';
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valid_out<='0';
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self_busy<='1';
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self_busy<='1';
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wakeup_reg<='0';
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state<=Halt;
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state<=Halt;
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elsif opcode(5 downto 4)="11" then
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elsif opcode(5 downto 4)="11" then
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valid_out<='1';
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valid_out<='1';
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self_busy<='1';
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self_busy<='1';
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state<=ContinueCjmp;
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state<=ContinueCjmp;
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Line 289... |
self_busy<='0';
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self_busy<='0';
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state<=Regular;
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state<=Regular;
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when ContinueInterrupt =>
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when ContinueInterrupt =>
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valid_out<='0';
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valid_out<='0';
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when Halt =>
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when Halt =>
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if interrupt_valid_i='1' then
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if interrupt_valid_i='1' or wakeup_i='1' or wakeup_reg='1' then
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self_busy<='0';
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self_busy<='0';
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state<=Regular;
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state<=Regular;
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end if;
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end if;
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end case;
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end case;
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end if;
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end if;
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