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https://opencores.org/ocsvn/lxp32/lxp32/trunk
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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entity platform is
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entity platform is
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generic(
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generic(
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CPU_DBUS_RMW: boolean;
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CPU_MUL_ARCH: string;
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MODEL_LXP32C: boolean;
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MODEL_LXP32C: boolean;
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THROTTLE_DBUS: boolean;
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THROTTLE_DBUS: boolean;
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THROTTLE_IBUS: boolean
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THROTTLE_IBUS: boolean
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);
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);
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port(
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port(
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cpu_irq<="00000"&coprocessor_irq&timer_elapsed&timer_elapsed;
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cpu_irq<="00000"&coprocessor_irq&timer_elapsed&timer_elapsed;
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gen_lxp32u: if not MODEL_LXP32C generate
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gen_lxp32u: if not MODEL_LXP32C generate
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lxp32u_top_inst: entity work.lxp32u_top(rtl)
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lxp32u_top_inst: entity work.lxp32u_top(rtl)
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generic map(
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generic map(
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DBUS_RMW=>false,
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DBUS_RMW=>CPU_DBUS_RMW,
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DIVIDER_EN=>true,
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DIVIDER_EN=>true,
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MUL_ARCH=>"dsp",
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MUL_ARCH=>CPU_MUL_ARCH,
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START_ADDR=>(others=>'0')
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START_ADDR=>(others=>'0')
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)
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)
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port map(
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port map(
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clk_i=>clk_i,
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clk_i=>clk_i,
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rst_i=>cpu_rst,
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rst_i=>cpu_rst,
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end generate;
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end generate;
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gen_lxp32c: if MODEL_LXP32C generate
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gen_lxp32c: if MODEL_LXP32C generate
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lxp32c_top_inst: entity work.lxp32c_top(rtl)
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lxp32c_top_inst: entity work.lxp32c_top(rtl)
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generic map(
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generic map(
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DBUS_RMW=>false,
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DBUS_RMW=>CPU_DBUS_RMW,
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DIVIDER_EN=>true,
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DIVIDER_EN=>true,
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IBUS_BURST_SIZE=>16,
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IBUS_BURST_SIZE=>16,
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IBUS_PREFETCH_SIZE=>32,
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IBUS_PREFETCH_SIZE=>32,
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MUL_ARCH=>"dsp",
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MUL_ARCH=>CPU_MUL_ARCH,
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START_ADDR=>(others=>'0')
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START_ADDR=>(others=>'0')
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)
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)
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port map(
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port map(
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clk_i=>clk_i,
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clk_i=>clk_i,
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rst_i=>cpu_rst,
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rst_i=>cpu_rst,
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