URL https://opencores.org/ocsvn/lzrw1-compressor-core/lzrw1-compressor-core/trunk

Subversion Repositories lzrw1-compressor-core

[/] [lzrw1-compressor-core/] [trunk/] [hw/] [xst_14_2/] [iseconfig/] [LZRWcompressor.projectmgr] - Diff between revs 2 and 3

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Rev 2	Rev 3
Line 7...	Line 7...


`2`	`2`


`LZRWcompressor.ucf (/home/lukas/e-/logic-analyzer/LZRW-compressor/hw/xst_14_2/LZRWcompressor.ucf)`	`CompressorTop - Behavioral (/home/lukas/e-/logic-analyzer/LZRW-compressor-OC/lzrw1-compressor-core/lzrw1-compressor-core/trunk/hw/HDL/CompressorTop.vhd)`

`0`	`0`
`0`	`0`
`000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000011e000000020000000000000000000000000000000064ffffffff0000008100000000000000020000011e0000000100000000000000000000000100000000`	`000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000011e000000020000000000000000000000000000000064ffffffff0000008100000000000000020000011e0000000100000000000000000000000100000000`
`true`	`true`
`LZRWcompressor.ucf (/home/lukas/e-/logic-analyzer/LZRW-compressor/hw/xst_14_2/LZRWcompressor.ucf)`	`CompressorTop - Behavioral (/home/lukas/e-/logic-analyzer/LZRW-compressor-OC/lzrw1-compressor-core/lzrw1-compressor-core/trunk/hw/HDL/CompressorTop.vhd)`



`1`	`1`
`Design Utilities`	`Design Utilities`
Line 65...	Line 65...
`Implement Design/Place & Route/Generate Post-Place & Route Static Timing`	`Implement Design/Place & Route/Generate Post-Place & Route Static Timing`
`Implement Design/Translate`	`Implement Design/Translate`
`User Constraints`	`User Constraints`


`Analyze Timing / Floorplan Design (PlanAhead)`	`Implement Design`

`8`	`4`
`0`	`0`
`000000ff000000000000000100000001000000000000000000000000000000000000000000000000e5000000010000000100000000000000000000000064ffffffff000000810000000000000001000000e50000000100000000`	`000000ff000000000000000100000001000000000000000000000000000000000000000000000000e5000000010000000100000000000000000000000064ffffffff000000810000000000000001000000e50000000100000000`
`false`	`false`
`Analyze Timing / Floorplan Design (PlanAhead)`	`Implement Design`



`2`	`2`
	`/CompressorTop_tb - TB \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor-OC\|lzrw1-compressor-core\|lzrw1-compressor-core\|trunk\|hw\|testbench\|CompressorTopTb.vhd`
`/CompressorTop_tb - TB \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|CompressorTopTb.vhd`	`/CompressorTop_tb - TB \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|CompressorTopTb.vhd`
`/CompressorTop_tb - TB \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|CompressorTopTb.vhd/DUT - CompressorTop - Behavioral/LZRWcompressorInst - LZRWcompressor - Behavioral`	`/CompressorTop_tb - TB \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|CompressorTopTb.vhd/DUT - CompressorTop - Behavioral/LZRWcompressorInst - LZRWcompressor - Behavioral`
`/HashTable_tb - tb D:\|e-\|logic-analyzer\|compression-test\|hw\|testbench\|TbHash.vhd`	`/HashTable_tb - tb D:\|e-\|logic-analyzer\|compression-test\|hw\|testbench\|TbHash.vhd`
`/HashTable_tb - tb G:\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|TbHash.vhd`	`/HashTable_tb - tb G:\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|TbHash.vhd`
	`/HashTable_tb - tb \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor-OC\|lzrw1-compressor-core\|lzrw1-compressor-core\|trunk\|hw\|testbench\|HastTb.vhd`
`/HashTable_tb - tb \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|TbHash.vhd`	`/HashTable_tb - tb \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|TbHash.vhd`
`/InputFIFO_tb - tb D:\|e-\|logic-analyzer\|compression-test\|hw\|testbench\|InputFIFOTb.vhd`	`/InputFIFO_tb - tb D:\|e-\|logic-analyzer\|compression-test\|hw\|testbench\|InputFIFOTb.vhd`
`/InputFIFO_tb - tb G:\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|InputFIFOTb.vhd`	`/InputFIFO_tb - tb G:\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|InputFIFOTb.vhd`
	`/InputFIFO_tb - tb \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor-OC\|lzrw1-compressor-core\|lzrw1-compressor-core\|trunk\|hw\|testbench\|InputFIFOTb.vhd`
`/InputFIFO_tb - tb \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|InputFIFOTb.vhd`	`/InputFIFO_tb - tb \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|InputFIFOTb.vhd`
`/LZRWcompressor_tb - tb D:\|e-\|logic-analyzer\|compression-test\|hw\|testbench\|LZRWcompressorTb.vhd`	`/LZRWcompressor_tb - tb D:\|e-\|logic-analyzer\|compression-test\|hw\|testbench\|LZRWcompressorTb.vhd`
`/LZRWcompressor_tb - tb G:\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|LZRWcompressorTb.vhd`	`/LZRWcompressor_tb - tb G:\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|LZRWcompressorTb.vhd`
	`/LZRWcompressor_tb - tb \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor-OC\|lzrw1-compressor-core\|lzrw1-compressor-core\|trunk\|hw\|testbench\|LZRWcompressorTb.vhd`
`/LZRWcompressor_tb - tb \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|LZRWcompressorTb.vhd`	`/LZRWcompressor_tb - tb \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|LZRWcompressorTb.vhd`
`/comparator_tb - Tb D:\|e-\|logic-analyzer\|compression-test\|hw\|HDL\|comparator_tb.vhd`	`/comparator_tb - Tb D:\|e-\|logic-analyzer\|compression-test\|hw\|HDL\|comparator_tb.vhd`
`/comparator_tb - Tb G:\|e-\|logic-analyzer\|LZRW-compressor\|hw\|HDL\|comparator_tb.vhd`	`/comparator_tb - Tb G:\|e-\|logic-analyzer\|LZRW-compressor\|hw\|HDL\|comparator_tb.vhd`
`/comparator_tb - Tb \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor\|hw\|HDL\|comparator_tb.vhd`	`/comparator_tb - Tb \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor\|hw\|HDL\|comparator_tb.vhd`
`/historyBuffer_tb - tb D:\|e-\|logic-analyzer\|compression-test\|hw\|HDL\|historyTb.vhd`	`/historyBuffer_tb - tb D:\|e-\|logic-analyzer\|compression-test\|hw\|HDL\|historyTb.vhd`
`/historyBuffer_tb - tb G:\|e-\|logic-analyzer\|LZRW-compressor\|hw\|HDL\|historyTb.vhd`	`/historyBuffer_tb - tb G:\|e-\|logic-analyzer\|LZRW-compressor\|hw\|HDL\|historyTb.vhd`
`/historyBuffer_tb - tb \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor\|hw\|HDL\|historyTb.vhd`	`/historyBuffer_tb - tb \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor\|hw\|HDL\|historyTb.vhd`
`/outputEncoder_tb - Tb D:\|e-\|logic-analyzer\|compression-test\|hw\|testbench\|outputEncoderTb.vhd`	`/outputEncoder_tb - Tb D:\|e-\|logic-analyzer\|compression-test\|hw\|testbench\|outputEncoderTb.vhd`
`/outputEncoder_tb - Tb G:\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|outputEncoderTb.vhd`	`/outputEncoder_tb - Tb G:\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|outputEncoderTb.vhd`
	`/outputEncoder_tb - Tb \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor-OC\|lzrw1-compressor-core\|lzrw1-compressor-core\|trunk\|hw\|testbench\|outputEncoderTb.vhd`
`/outputEncoder_tb - Tb \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|outputEncoderTb.vhd`	`/outputEncoder_tb - Tb \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|outputEncoderTb.vhd`
`/outputFIFO_tb - tb D:\|e-\|logic-analyzer\|compression-test\|hw\|testbench\|outputFIFOTb.vhd`	`/outputFIFO_tb - tb D:\|e-\|logic-analyzer\|compression-test\|hw\|testbench\|outputFIFOTb.vhd`
`/outputFIFO_tb - tb G:\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|outputFIFOTb.vhd`	`/outputFIFO_tb - tb G:\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|outputFIFOTb.vhd`
`/outputFIFO_tb - tb \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|outputFIFOTb.vhd`	`/outputFIFO_tb - tb \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|outputFIFOTb.vhd`


`Unassigned User Library Modules`	`LZRWcompressor_tb - tb (/home/lukas/e-/logic-analyzer/LZRW-compressor-OC/lzrw1-compressor-core/lzrw1-compressor-core/trunk/hw/testbench/LZRWcompressorTb.vhd)`

`0`	`0`
`0`	`0`
`000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000018e000000020000000000000000000000000000000064ffffffff0000008100000000000000020000018e0000000100000000000000000000000100000000`	`000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000018e000000020000000000000000000000000000000064ffffffff0000008100000000000000020000018e0000000100000000000000000000000100000000`
`false`	`false`
`Unassigned User Library Modules`	`LZRWcompressor_tb - tb (/home/lukas/e-/logic-analyzer/LZRW-compressor-OC/lzrw1-compressor-core/lzrw1-compressor-core/trunk/hw/testbench/LZRWcompressorTb.vhd)`



`1`	`1`
`Design Utilities`	`Design Utilities`
Line 132...	Line 137...

`Simulate Behavioral Model`	`Simulate Behavioral Model`

`0`	`0`
`0`	`0`
`000000ff000000000000000100000001000000000000000000000000000000000000000000000001ab000000010000000100000000000000000000000064ffffffff000000810000000000000001000001ab0000000100000000`	`000000ff000000000000000100000001000000000000000000000000000000000000000000000000f4000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f40000000100000000`
`false`	`false`
`Simulate Behavioral Model`	`Simulate Behavioral Model`

`000000ff0000000000000002000000c20000008b01000000060100000002`	`000000ff0000000000000002000000c20000008b01000000060100000002`
`Behavioral Simulation`	`Implementation`


`1`	`1`


`Edit Constraints (Text)`

`0`	`0`
`0`	`0`
`000000ff000000000000000100000001000000000000000000000000000000000000000000000000f4000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f40000000100000000`	`000000ff000000000000000100000001000000000000000000000000000000000000000000000000f4000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f40000000100000000`
`false`	`false`
`Edit Constraints (Text)`

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Subversion Repositories lzrw1-compressor-core

[/] [lzrw1-compressor-core/] [trunk/] [hw/] [xst_14_2/] [iseconfig/] [LZRWcompressor.projectmgr] - Diff between revs 2 and 3