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/*
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/*
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* Simply RISC M1 Core Testbench
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* Simply RISC M1 Core Testbench
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*/
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*/
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`include "ddr_include.v"
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module testbench();
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module testbench();
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reg sys_clock_i, sys_reset_i;
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reg[31:0] sys_irq_i;
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m1_core core_0(sys_clock_i, sys_reset_i, sys_irq_i);
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/*
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* Registers
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*/
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// System
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reg sys_clock;
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reg sys_reset;
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/*
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* Wires
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*/
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// VGA Port
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wire vga_rgb_r;
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wire vga_rgb_g;
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wire vga_rgb_b;
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wire vga_hsync;
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wire vga_vsync;
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// PS/2 Keyboard interface
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wire ps2_keyboard_clock;
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wire ps2_keyboard_data;
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wire[7:0] received_char;
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wire char_valid;
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// DDR Port
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wire ddr_clk;
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wire ddr_clk_n;
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wire ddr_clk_fb = ddr_clk;
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wire ddr_ras_n;
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wire ddr_cas_n;
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wire ddr_we_n;
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wire ddr_cke;
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wire ddr_cs_n;
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wire[`A_RNG] ddr_a;
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wire[`BA_RNG] ddr_ba;
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wire[`DQ_RNG] ddr_dq;
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wire[`DQS_RNG] ddr_dqs;
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wire[`DM_RNG] ddr_dm;
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/*
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* Module instances
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*/
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// DUT (Design Under Test)
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spartan3esk_top spartan3esk_top_0 (
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// System
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.sys_clock_i(sys_clock),
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.sys_reset_i(sys_reset),
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// VGA Port
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.vga_rgb_r_o(vga_rgb_r),
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.vga_rgb_g_o(vga_rgb_g),
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.vga_rgb_b_o(vga_rgb_b),
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.vga_hsync_o(vga_hsync),
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.vga_vsync_o(vga_vsync),
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// PS/2 Keyboard interface
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.ps2_keyboard_clock_io(ps2_keyboard_clock),
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.ps2_keyboard_data_io(ps2_keyboard_data),
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// DDR Port
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.ddr_clk(ddr_clk),
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.ddr_clk_n(ddr_clk_n),
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.ddr_clk_fb(ddr_clk_fb),
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.ddr_ras_n(ddr_ras_n),
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.ddr_cas_n(ddr_cas_n),
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.ddr_we_n(ddr_we_n),
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.ddr_cke(ddr_cke),
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.ddr_cs_n(ddr_cs_n),
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.ddr_a(ddr_a),
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.ddr_ba(ddr_ba),
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.ddr_dq(ddr_dq),
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.ddr_dqs(ddr_dqs),
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.ddr_dm(ddr_dm)
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);
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// PS/2 Keyboard model
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ps2_keyboard_model ps2_keyboard_model_0 (
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.kbd_clk_io(ps2_keyboard_clock),
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.kbd_data_io(ps2_keyboard_data),
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.last_char_received_o(received_char),
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.char_valid_o(char_valid)
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);
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// DDR model (Micron mt46v16m16)
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ddr ddr_0 (
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.Dq(ddr_dq),
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.Dqs(ddr_dqs),
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.Addr(ddr_a),
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.Ba(ddr_ba),
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.Clk(ddr_clk),
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.Clk_n(ddr_clk_n),
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.Cke(ddr_cke),
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.Cs_n(ddr_cs_n),
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.Ras_n(ddr_ras_n),
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.Cas_n(ddr_cas_n),
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.We_n(ddr_we_n),
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.Dm(ddr_dm)
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);
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/*
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* Sequential logic
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*/
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always #1 sys_clock_i = ~sys_clock_i;
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// Clock
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always #10 sys_clock = !sys_clock;
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// Reset
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initial begin
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initial begin
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// Display start message
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// Display start message
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$display("INFO: TBENCH(%m): Starting Simply RISC M1 Core simulation...");
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$display("INFO: TBENCH(%m): Starting Simply RISC M1 Core simulation...");
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// Create VCD trace file
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// Create VCD trace file
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$dumpfile("trace.vcd");
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$dumpfile("trace.vcd");
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$dumpvars();
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$dumpvars();
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// Run the simulation
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// Run the simulation
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sys_clock_i <= 1;
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sys_clock <= 1;
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sys_reset_i <= 1;
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sys_reset <= 1;
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#5
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sys_reset_i <= 0;
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#1000
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#1000
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sys_reset <= 0;
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#99000
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$display("INFO: TBENCH(%m): Completed Simply RISC M1 Core simulation!");
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$display("INFO: TBENCH(%m): Completed Simply RISC M1 Core simulation!");
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$finish;
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$finish;
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end
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end
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