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[/] [m1_core/] [trunk/] [hdl/] [filelist.dc] - Diff between revs 2 and 12

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# Synthesis script for dc_shell (Tcl mode)
# Synthesis script for dc_shell (Tcl mode)
 
 
# Analyze
# Analyze
 
 
set search_path [concat [list /home/fabrizio/m1_core/hdl/rtl/m1_cpu] $search_path]
set search_path [concat [list /home/fabrizio/m1_core/hdl/rtl/m1_cpu] $search_path]
analyze -format verilog ~/m1_core/hdl/rtl/m1_cpu/m1_alu.v
analyze -format verilog ~/m1_core/hdl/rtl/m1_cpu/m1_alu.v
analyze -format verilog ~/m1_core/hdl/rtl/m1_cpu/m1_cpu.v
analyze -format verilog ~/m1_core/hdl/rtl/m1_cpu/m1_cpu.v
 
 
# Elaborate
# Technology-independent elaboration and linking
elaborate m1_cpu
 
 
set active_design m1_cpu
 
elaborate $active_design
 
current_design $active_design
link
link
uniquify
uniquify
check_design
 
 
 
# Constraints
# Constraints and mapping on target library
create_clock -name "sys_clock_i" -period 2.0 -waveform {0 1.0} [get_ports "sys_clock_i"]
 
set_dont_touch_network [get_clocks "sys_clock_i"]
 
set_input_delay 1.25 -max -rise -clock "sys_clock_i" [get_ports "sys_reset_i"]
 
set_input_delay 1.25 -max -fall -clock "sys_clock_i" [get_ports "sys_reset_i"]
 
set_output_delay 1.25 -clock sys_clock_i -max -rise [all_outputs]
 
set_output_delay 1.25 -clock sys_clock_i -max -fall [all_outputs]
 
set_wire_load_mode "enclosed"
 
 
 
# Compile
 
compile -map_effort low
 
write -format db -hierarchy -output m1_cpu.db
 
write -format verilog -hierarchy -output m1_cpu.v
 
 
 
# Report
 
report_area > report_area.txt
 
report_timing > report_timing.txt
 
report_constraint -all_violators > report_constraint.txt
 
 
 
quit
 
 
 
 
create_clock -period 4.0 -waveform [list 0 2.0] sys_clock_i
 
set_input_delay 2.0 -clock sys_clock_i -max [all_inputs]
 
set_output_delay 1.0 -clock sys_clock_i -max [all_outputs]
 
set_dont_touch_network [list sys_clock_i sys_reset_i]
 
set_drive 0 [list sys_clock_i sys_reset_i]
 
set_wire_load_mode enclosed
 
set_max_area 0
 
set_fix_multiple_port_nets -buffer_constants -all
 
compile
 
 
 
# Export the mapped design
 
 
 
remove_unconnected_ports [find -hierarchy cell {"*"}]
 
write -format ddc -hierarchy -output $active_design.ddc
 
write -format verilog -hierarchy -output $active_design.sv
 
 
 
# Report area and timing
 
 
 
report_area -hierarchy > report_area.rpt
 
report_timing > report_timing.rpt
 
report_constraint -all_violators > report_constraint.rpt
 
 
 
quit
 
 

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