URL https://opencores.org/ocsvn/m1_core/m1_core/trunk

Subversion Repositories m1_core

[/] [m1_core/] [trunk/] [hdl/] [rtl/] [m1_core/] [m1_defs.vh] - Diff between revs 33 and 46

Rev 33	Rev 46
Line 13...	Line 13...
`define SIZE_HALF 3'b001	`define SIZE_HALF 3'b001
`define SIZE_WORD 3'b011	`define SIZE_WORD 3'b011
`define SIZE_LEFT 3'b100	`define SIZE_LEFT 3'b100
`define SIZE_RIGHT 3'b101	`define SIZE_RIGHT 3'b101

	`// System Configuration Coprocessor (CP0) registers for TLB-less systems`
	`define SYSCON_BADVADDR 8
	`define SYSCON_STATUS 12
	`define SYSCON_CAUSE 13
	`define SYSCON_EPC 14
	`define SYSCON_PRID 15

`// Opcodes (ordered by binary value)`	`// Opcodes (ordered by binary value)`
`define OPCODE_SPECIAL 6'b000000 // SPECIAL instruction class	`define OPCODE_SPECIAL 6'b000000 // SPECIAL instruction class
`define OPCODE_BCOND 6'b000001 // BCOND instruction class	`define OPCODE_BCOND 6'b000001 // BCOND instruction class
`define OPCODE_J 6'b000010 // Jump	`define OPCODE_J 6'b000010 // Jump
`define OPCODE_JAL 6'b000011 // Jump and link	`define OPCODE_JAL 6'b000011 // Jump and link