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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// Modules contained in this file:
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// Modules contained in this file:
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// ADDR_UNIT generates data access addresses and controls data cache operation
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// ADDR_UNIT generates data access addresses and controls data cache operation
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//
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//
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module ADDR_UNIT ( BCLK, BRESET, READ, WRITE, LDEA, NEWACC, CLRMSW, POST, DISP_OK, FULLACC, SRC2SEL,
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module ADDR_UNIT ( BCLK, BRESET, READ, WRITE, LDEA, NEWACC, CLRMSW, POST, DISP_OK, FULLACC, SRC2SEL, INDEX, ASIZE, SRC1, SRC2, BWD,
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DISP, PC_ARCHI, PC_ICACHE, IO_READY, ACC_STAT, MMU_UPDATE, IC_TEX, ABO_STAT, ADIVAR, RWVAL_1,
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DISP, PC_ARCHI, PC_ICACHE, IO_READY, ACC_STAT, MMU_UPDATE, IC_TEX, ABO_STAT, ADIVAR, RWVAL_1, OP_RMW, PHASE_17,
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NO_TRAP, FPU_TRAP, READ_OUT, WRITE_OUT, ZTEST, RMW, VADR, ADDR, SIZE, PACKET, ACC_DONE, ABORT
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NO_TRAP, FPU_TRAP, READ_OUT, WRITE_OUT, ZTEST, RMW, VADR, ADDR, SIZE, PACKET, ACC_DONE, ABORT, REG_OUT, BITSEL );
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input BCLK,BRESET;
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input BCLK,BRESET;
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input READ,WRITE,LDEA;
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input READ,WRITE,LDEA;
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input NEWACC;
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input NEWACC;
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input CLRMSW,POST,FULLACC;
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input CLRMSW,POST,FULLACC;
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assign acc_ok = ACC_STAT[0] & ~pg_op;
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assign acc_ok = ACC_STAT[0] & ~pg_op;
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assign acc_pass = ACC_STAT[0] & ZTEST;
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assign acc_pass = ACC_STAT[0] & ZTEST;
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always @(posedge BCLK) ABORT <= acc_err; // Signal to Steuerung - only a pulse
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always @(posedge BCLK) ABORT <= acc_err; // Signal to Steuerung - only a pulse
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always @(posedge BCLK) if (acc_err) tex_feld <= ACC_STAT[3] ? 2'b11 : {~ACC_STAT[2],ACC_STAT[2]}; /
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always @(posedge BCLK) if (acc_err) tex_feld <= ACC_STAT[3] ? 2'b11 : {~ACC_STAT[2],ACC_STAT[2]}; // for MSR
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always @(posedge BCLK) if (acc_err) u_ddt <= {RMW,ABO_STAT[1],(WRITE_OUT | ZTEST)};
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always @(posedge BCLK) if (acc_err) u_ddt <= {RMW,ABO_STAT[1],(WRITE_OUT | ZTEST)};
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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always @(SRC2SEL or CLRMSW or SRC2 or PC_ARCHI or ea_reg)
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always @(SRC2SEL or CLRMSW or SRC2 or PC_ARCHI or ea_reg)
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case (SRC2SEL)
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case (SRC2SEL)
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2'b00 : source2 = {(CLRMSW ? 16'h0000 : SRC2[31:16]),SRC2[15:0]}; // base reg, External Addressi
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2'b00 : source2 = {(CLRMSW ? 16'h0000 : SRC2[31:16]),SRC2[15:0]}; // base reg, External Addressing with MOD
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2'b01 : source2 = PC_ARCHI; // PC relative
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2'b01 : source2 = PC_ARCHI; // PC relative
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2'b10 : source2 = 32'h0; // Absolute Addressing
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2'b10 : source2 = 32'h0; // Absolute Addressing
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2'b11 : source2 = ea_reg; // REUSE : 2. TOS
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2'b11 : source2 = ea_reg; // REUSE : 2. TOS
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endcase
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endcase
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assign index_sel = POST ? 4'h0 : INDEX; // Alternative application of Index for POST Adder : POP fr
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assign index_sel = POST ? 4'h0 : INDEX; // Alternative application of Index for POST Adder : POP from Stack
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always @(BWD or SRC1)
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always @(BWD or SRC1)
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casex (BWD)
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casex (BWD)
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2'b00 : sign_ext_src1 = {{24{SRC1[7]}}, SRC1[7:0]}; // Byte
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2'b00 : sign_ext_src1 = {{24{SRC1[7]}}, SRC1[7:0]}; // Byte
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2'b01 : sign_ext_src1 = {{16{SRC1[15]}},SRC1[15:0]}; // Word
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2'b01 : sign_ext_src1 = {{16{SRC1[15]}},SRC1[15:0]}; // Word
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assign reg_adder = source2 + index_val; // SRC2 allows simple MOV with SRC1
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assign reg_adder = source2 + index_val; // SRC2 allows simple MOV with SRC1
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assign final_addr = reg_adder + DISP; // That's the final access address
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assign final_addr = reg_adder + DISP; // That's the final access address
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always @(posedge BCLK) if (LDEA && (index_sel[3:2] == 2'b11)) BITSEL <= SRC1[2:0]; // for Bit Opcod
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always @(posedge BCLK) if (LDEA && (index_sel[3:2] == 2'b11)) BITSEL <= SRC1[2:0]; // for Bit Opcodes in I_PFAD
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always @(INDEX) // SP POP Operation & String Backward
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always @(INDEX) // SP POP Operation & String Backward
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case (INDEX[2:0])
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case (INDEX[2:0])
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3'b000 : tos_offset = 32'h0000_0001;
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3'b000 : tos_offset = 32'h0000_0001;
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3'b001 : tos_offset = 32'h0000_0002;
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3'b001 : tos_offset = 32'h0000_0002;
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end
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end
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assign ADDR = ea_reg; // used for ADDR opcode and TOS Addressing
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assign ADDR = ea_reg; // used for ADDR opcode and TOS Addressing
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// This pulse stores all parameters of access
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// This pulse stores all parameters of access
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assign init_acc = ((FULLACC ? (NEWACC & acc_ende) : acc_ende) | ~acc_run) & DISP_OK & (READ | WRITE
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assign init_acc = ((FULLACC ? (NEWACC & acc_ende) : acc_ende) | ~acc_run) & DISP_OK & (READ | WRITE) & ~ABORT & NO_TRAP;
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assign fa_out = init_acc | ADIVAR; // special case for LMR IVAR,...
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assign fa_out = init_acc | ADIVAR; // special case for LMR IVAR,...
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always @(fa_out or acc_ok or final_addr or qw_align or pg_op or pg_areg or vadr_reg or next_vadr)
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always @(fa_out or acc_ok or final_addr or qw_align or pg_op or pg_areg or vadr_reg or next_vadr)
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casex ({fa_out,acc_ok})
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casex ({fa_out,acc_ok})
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READ_OUT <= init_acc ? (READ & ~RWVAL_1) : (READ_OUT & ~acc_ende & ~acc_err);
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READ_OUT <= init_acc ? (READ & ~RWVAL_1) : (READ_OUT & ~acc_ende & ~acc_err);
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always @(posedge BCLK or negedge BRESET)
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always @(posedge BCLK or negedge BRESET)
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if (!BRESET) write_reg <= 1'b0;
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if (!BRESET) write_reg <= 1'b0;
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else
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else
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write_reg <= (init_acc ? (WRITE & ~RWVAL_1 & ~pg_test) : (write_reg & ~acc_ende & ~acc_err & ~FPU
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write_reg <= (init_acc ? (WRITE & ~RWVAL_1 & ~pg_test) : (write_reg & ~acc_ende & ~acc_err & ~FPU_TRAP)) | do_wr;
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assign WRITE_OUT = write_reg & ~FPU_TRAP;
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assign WRITE_OUT = write_reg & ~FPU_TRAP;
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// Special case for RDVAL and WRVAL
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// Special case for RDVAL and WRVAL
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always @(posedge BCLK or negedge BRESET)
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always @(posedge BCLK or negedge BRESET)
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if (!BRESET) ZTEST <= 1'b0;
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if (!BRESET) ZTEST <= 1'b0;
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else
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else
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ZTEST <= pg_op ? (~ZTEST | (~acc_pass & ~acc_err)) : (init_acc ? RWVAL_1 : (ZTEST & ~acc_ende &
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ZTEST <= pg_op ? (~ZTEST | (~acc_pass & ~acc_err)) : (init_acc ? RWVAL_1 : (ZTEST & ~acc_ende & ~acc_err));
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always @(posedge BCLK or negedge BRESET)
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always @(posedge BCLK or negedge BRESET)
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if (!BRESET) RMW <= 1'b0;
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if (!BRESET) RMW <= 1'b0;
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else
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else
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RMW <= init_acc ? (OP_RMW & PHASE_17) : (RMW & ~acc_ende & ~acc_err);
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RMW <= init_acc ? (OP_RMW & PHASE_17) : (RMW & ~acc_ende & ~acc_err);
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Line 276... |
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always @(posedge BCLK) if (init_acc) SIZE <= ASIZE;
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always @(posedge BCLK) if (init_acc) SIZE <= ASIZE;
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assign inc_pack = (PACKET[1:0] == 2'b00) ? 2'b10 : {(SIZE[1] ^ SIZE[0]),(SIZE[1] & SIZE[0])};
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assign inc_pack = (PACKET[1:0] == 2'b00) ? 2'b10 : {(SIZE[1] ^ SIZE[0]),(SIZE[1] & SIZE[0])};
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// Counter for data packets 1 to 3 : special case aligned QWORD : only 2 packets. Additionally star
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// Counter for data packets 1 to 3 : special case aligned QWORD : only 2 packets. Additionally start address in bits 1 und 0.
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// special coding (00) -> [01] -> (10) , [01] optional by QWORD and (10) shows always the end
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// special coding (00) -> [01] -> (10) , [01] optional by QWORD and (10) shows always the end
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always @(posedge BCLK)
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always @(posedge BCLK)
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if (init_acc) PACKET <= {2'b00,final_addr[1:0]};
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if (init_acc) PACKET <= {2'b00,final_addr[1:0]};
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else
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else
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if (acc_ok) PACKET <= PACKET + {inc_pack,2'b00};
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if (acc_ok) PACKET <= PACKET + {inc_pack,2'b00};
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5'b10_1_xx : acc_ende = acc_ok; // 2 packets
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5'b10_1_xx : acc_ende = acc_ok; // 2 packets
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5'b11_1_xx : acc_ende = acc_ok; // QWord at least 2 packets
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5'b11_1_xx : acc_ende = acc_ok; // QWord at least 2 packets
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default : acc_ende = 1'b0;
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default : acc_ende = 1'b0;
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endcase
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endcase
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assign in_page = (vadr_reg[11:3] != 9'h1FF); // Access inside a page ? During WRITE address is incr
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assign in_page = (vadr_reg[11:3] != 9'h1FF); // Access inside a page ? During WRITE address is increasing : 1. LSD 2. MSD
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always @(SIZE or vadr_reg or in_page or PACKET)
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always @(SIZE or vadr_reg or in_page or PACKET)
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casex (SIZE)
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casex (SIZE)
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2'b01 : frueh_ok = (vadr_reg[3:2] != 2'b11); //Word
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2'b01 : frueh_ok = (vadr_reg[3:2] != 2'b11); //Word
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2'b10 : frueh_ok = (vadr_reg[3:2] != 2'b11); //DWord
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2'b10 : frueh_ok = (vadr_reg[3:2] != 2'b11); //DWord
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2'b11 : frueh_ok = (PACKET[1:0] == 2'b00) ? (~vadr_reg[3] | ~vadr_reg[2]) : ((PACKET[3:2] == 2'b
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2'b11 : frueh_ok = (PACKET[1:0] == 2'b00) ? (~vadr_reg[3] | ~vadr_reg[2]) : ((PACKET[3:2] == 2'b01) & (vadr_reg[3:2] != 2'b11));
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default : frueh_ok = 1'b1; // Byte don't case
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default : frueh_ok = 1'b1; // Byte don't case
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endcase
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endcase
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assign all_ok = SIZE[1] ? (PACKET[1:0] == 2'b00) : (PACKET[1:0] != 2'b11); // for DWord : Word
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assign all_ok = SIZE[1] ? (PACKET[1:0] == 2'b00) : (PACKET[1:0] != 2'b11); // for DWord : Word
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always @(SIZE or READ_OUT or frueh_ok or PACKET or all_ok or io_acc or acc_ok or qwa_flag or io_rdy
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always @(SIZE or READ_OUT or frueh_ok or PACKET or all_ok or io_acc or acc_ok or qwa_flag or io_rdy or ca_hit)
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casex ({SIZE,READ_OUT,frueh_ok,PACKET[3],io_acc,all_ok})
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casex ({SIZE,READ_OUT,frueh_ok,PACKET[3],io_acc,all_ok})
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7'b00_xxxx_x : acc_step = acc_ok; // Byte, all ok
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7'b00_xxxx_x : acc_step = acc_ok; // Byte, all ok
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//
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//
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7'b01_xxxx_1 : acc_step = acc_ok; // Word : aligned access , only 1 packet
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7'b01_xxxx_1 : acc_step = acc_ok; // Word : aligned access , only 1 packet
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7'b01_1x1x_0 : acc_step = acc_ok; // READ must wait for all data
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7'b01_1x1x_0 : acc_step = acc_ok; // READ must wait for all data
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| Line 324... |
Line 324... |
7'b10_001x_0 : acc_step = acc_ok; // WRITE Adr. ist not perfect and waits for last packet
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7'b10_001x_0 : acc_step = acc_ok; // WRITE Adr. ist not perfect and waits for last packet
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7'b10_01xx_0 : acc_step = acc_ok; // WRITE Adr. perfect - acc_step after 1. packet
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7'b10_01xx_0 : acc_step = acc_ok; // WRITE Adr. perfect - acc_step after 1. packet
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// fast QWord READ : there would be a 2. acc_step if not ~PACK...
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// fast QWord READ : there would be a 2. acc_step if not ~PACK...
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7'b11_1xxx_x : acc_step = acc_ok & ( (qwa_flag & ~io_rdy & ca_hit) ? ~PACKET[3] : PACKET[3] );
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7'b11_1xxx_x : acc_step = acc_ok & ( (qwa_flag & ~io_rdy & ca_hit) ? ~PACKET[3] : PACKET[3] );
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7'b11_0x1x_x : acc_step = acc_ok;
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7'b11_0x1x_x : acc_step = acc_ok;
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7'b11_0100_x : acc_step = acc_ok; // WRITE Adr. perfect - acc_step after 1. packet if not io_a
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7'b11_0100_x : acc_step = acc_ok; // WRITE Adr. perfect - acc_step after 1. packet if not io_acc
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default : acc_step = 1'b0;
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default : acc_step = 1'b0;
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endcase
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endcase
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// There is a 2. acc_step if packet (10) - this must be suppressed
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// There is a 2. acc_step if packet (10) - this must be suppressed
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always @(posedge BCLK or negedge BRESET)
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always @(posedge BCLK or negedge BRESET)
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| Line 336... |
Line 336... |
else no_done <= (~acc_ende & acc_step) | (no_done & ~(acc_run & acc_ende));
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else no_done <= (~acc_ende & acc_step) | (no_done & ~(acc_run & acc_ende));
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// The final DONE Multiplexer
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// The final DONE Multiplexer
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assign ACC_DONE = acc_run ? (acc_step & ~no_done) : ea_ok;
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assign ACC_DONE = acc_run ? (acc_step & ~no_done) : ea_ok;
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always @(posedge BCLK) reg_out_i <= ~acc_step & BRESET & ((qwa_flag & (io_rdy | ~ca_hit) & acc_ok)
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always @(posedge BCLK) reg_out_i <= ~acc_step & BRESET & ((qwa_flag & (io_rdy | ~ca_hit) & acc_ok) | reg_out_i);
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always @(posedge BCLK) io_rdy <= IO_READY & (WRITE_OUT | READ_OUT);
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always @(posedge BCLK) io_rdy <= IO_READY & (WRITE_OUT | READ_OUT);
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always @(posedge BCLK) next_reg <= (acc_step & ~qwa_flag) & (SIZE == 2'b11);
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always @(posedge BCLK) next_reg <= (acc_step & ~qwa_flag) & (SIZE == 2'b11);
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assign REG_OUT = reg_out_i | next_reg;
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assign REG_OUT = reg_out_i | next_reg;
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