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//
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//
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// This file is part of the M32632 project
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// This file is part of the M32632 project
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// http://opencores.org/project,m32632
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// http://opencores.org/project,m32632
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//
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//
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// Filename: ADDR_UNIT.v
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// Filename: ADDR_UNIT.v
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// Version: 1.0
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// Version: 1.1 bug fix
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// Date: 30 May 2015
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// History: 1.0 first release of 30 Mai 2015
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// Date: 7 October 2015
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//
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//
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// Copyright (C) 2015 Udo Moeller
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// Copyright (C) 2015 Udo Moeller
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module ADDR_UNIT ( BCLK, BRESET, READ, WRITE, LDEA, NEWACC, CLRMSW, POST, DISP_OK, FULLACC, SRC2SEL, INDEX, ASIZE, SRC1, SRC2, BWD,
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module ADDR_UNIT ( BCLK, BRESET, READ, WRITE, LDEA, NEWACC, CLRMSW, POST, DISP_OK, FULLACC, SRC2SEL, INDEX, ASIZE, SRC1, SRC2, BWD,
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DISP, PC_ARCHI, PC_ICACHE, IO_READY, ACC_STAT, MMU_UPDATE, IC_TEX, ABO_STAT, ADIVAR, RWVAL_1, OP_RMW, PHASE_17,
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DISP, PC_ARCHI, PC_ICACHE, IO_READY, ACC_STAT, MMU_UPDATE, IC_TEX, ABO_STAT, ADIVAR, RWVAL_1, OP_RMW, PHASE_17,
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NO_TRAP, FPU_TRAP, READ_OUT, WRITE_OUT, ZTEST, RMW, VADR, ADDR, SIZE, PACKET, ACC_DONE, ABORT, REG_OUT, BITSEL );
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NO_TRAP, FPU_TRAP, READ_OUT, WRITE_OUT, ZTEST, RMW, VADR, ADDR, SIZE, PACKET, ACC_DONE, ABORT, REG_OUT, BITSEL,
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QWATWO );
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input BCLK,BRESET;
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input BCLK,BRESET;
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input READ,WRITE,LDEA;
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input READ,WRITE,LDEA;
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input NEWACC;
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input NEWACC;
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input CLRMSW,POST,FULLACC;
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input CLRMSW,POST,FULLACC;
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output [3:0] PACKET;
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output [3:0] PACKET;
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output ACC_DONE;
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output ACC_DONE;
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output ABORT;
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output ABORT;
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output REG_OUT;
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output REG_OUT;
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output [2:0] BITSEL;
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output [2:0] BITSEL;
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output reg QWATWO;
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reg [31:0] VADR;
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reg [31:0] VADR;
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reg READ_OUT,write_reg,ZTEST,RMW;
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reg READ_OUT,write_reg,ZTEST,RMW;
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reg [1:0] SIZE;
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reg [1:0] SIZE;
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reg [3:0] PACKET;
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reg [3:0] PACKET;
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else no_done <= (~acc_ende & acc_step) | (no_done & ~(acc_run & acc_ende));
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else no_done <= (~acc_ende & acc_step) | (no_done & ~(acc_run & acc_ende));
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// The final DONE Multiplexer
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// The final DONE Multiplexer
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assign ACC_DONE = acc_run ? (acc_step & ~no_done) : ea_ok;
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assign ACC_DONE = acc_run ? (acc_step & ~no_done) : ea_ok;
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// Bugfix of 7.October 2015
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always @(posedge BCLK) QWATWO <= acc_run & acc_ok & qwa_flag & ~io_rdy & ca_hit & ~PACKET[3] & (SIZE == 2'b11) & READ_OUT & ~no_done;
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always @(posedge BCLK) reg_out_i <= ~acc_step & BRESET & ((qwa_flag & (io_rdy | ~ca_hit) & acc_ok) | reg_out_i);
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always @(posedge BCLK) reg_out_i <= ~acc_step & BRESET & ((qwa_flag & (io_rdy | ~ca_hit) & acc_ok) | reg_out_i);
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always @(posedge BCLK) io_rdy <= IO_READY & (WRITE_OUT | READ_OUT);
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always @(posedge BCLK) io_rdy <= IO_READY & (WRITE_OUT | READ_OUT);
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always @(posedge BCLK) next_reg <= (acc_step & ~qwa_flag) & (SIZE == 2'b11);
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always @(posedge BCLK) next_reg <= (acc_step & ~qwa_flag) & (SIZE == 2'b11);
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