OpenCores
URL https://opencores.org/ocsvn/m32632/m32632/trunk

Subversion Repositories m32632

[/] [m32632/] [trunk/] [rtl/] [ADDR_UNIT.v] - Diff between revs 12 and 16

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 12 Rev 16
Line 2... Line 2...
//
//
// This file is part of the M32632 project
// This file is part of the M32632 project
// http://opencores.org/project,m32632
// http://opencores.org/project,m32632
//
//
// Filename: ADDR_UNIT.v
// Filename: ADDR_UNIT.v
// Version:  1.1 bug fix
// Version:  1.2 bug fix
// History:  1.0 first release of 30 Mai 2015
// History:  1.1 bug fix release of 7 October 2015
// Date:     7 October 2015
//           1.0 first release of 30 Mai 2015
 
// Date:     8 March 2016
//
//
// Copyright (C) 2015 Udo Moeller
// Copyright (C) 2015 Udo Moeller
// 
// 
// This source file may be used and distributed without 
// This source file may be used and distributed without 
// restriction provided that this copyright statement is not 
// restriction provided that this copyright statement is not 
Line 156... Line 157...
                  default : sign_ext_src1 = SRC1;
                  default : sign_ext_src1 = SRC1;
                endcase
                endcase
 
 
        always @(index_sel or sign_ext_src1 or SRC1)
        always @(index_sel or sign_ext_src1 or SRC1)
                casex (index_sel)
                casex (index_sel)
                  4'b1_0xx : index_val = sign_ext_src1; // für CASE
                  4'b1_0xx : index_val = sign_ext_src1; // f�r CASE
                  4'b1_1xx : index_val = {{ 3{sign_ext_src1[31]}},sign_ext_src1[31:3]}; // for Bit Opcodes
                  4'b1_1xx : index_val = {{ 3{sign_ext_src1[31]}},sign_ext_src1[31:3]}; // for Bit Opcodes
                  4'b0_100 : index_val = SRC1;
                  4'b0_100 : index_val = SRC1;
                  4'b0_101 : index_val = {SRC1[30:0],1'b0};
                  4'b0_101 : index_val = {SRC1[30:0],1'b0};
                  4'b0_110 : index_val = {SRC1[29:0],2'b00};
                  4'b0_110 : index_val = {SRC1[29:0],2'b00};
                  4'b0_111 : index_val = {SRC1[28:0],3'b000};
                  4'b0_111 : index_val = {SRC1[28:0],3'b000};
Line 317... Line 318...
                casex ({SIZE,READ_OUT,frueh_ok,PACKET[3],io_acc,all_ok})
                casex ({SIZE,READ_OUT,frueh_ok,PACKET[3],io_acc,all_ok})
                  7'b00_xxxx_x : acc_step = acc_ok;     // Byte, all ok
                  7'b00_xxxx_x : acc_step = acc_ok;     // Byte, all ok
                //
                //
                  7'b01_xxxx_1 : acc_step = acc_ok;     // Word :       aligned access , only 1 packet
                  7'b01_xxxx_1 : acc_step = acc_ok;     // Word :       aligned access , only 1 packet
                  7'b01_1x1x_0 : acc_step = acc_ok;     //                      READ must wait for all data
                  7'b01_1x1x_0 : acc_step = acc_ok;     //                      READ must wait for all data
                  7'b01_001x_0 : acc_step = acc_ok;     //                      WRITE Adr. ist not perfect and waits for last packet
                  7'b01_0x1x_0 : acc_step = acc_ok;     //                      WRITE Adr. is not perfect and waits for last packet
                  7'b01_01xx_0 : acc_step = acc_ok;     //                      WRITE Adr. perfect - acc_step after 1. packet
                  7'b01_0100_0 : acc_step = acc_ok;     //                      WRITE Adr. perfect - acc_step after 1. packet if not io_acc
                //
                //
                  7'b10_xxxx_1 : acc_step = acc_ok;     // DWord :      aligned access , only 1 packet
                  7'b10_xxxx_1 : acc_step = acc_ok;     // DWord :      aligned access , only 1 packet
                  7'b10_1x1x_0 : acc_step = acc_ok;     //                      READ must wait for all data
                  7'b10_1x1x_0 : acc_step = acc_ok;     //                      READ must wait for all data
                  7'b10_001x_0 : acc_step = acc_ok;     //                      WRITE Adr. ist not perfect and waits for last packet
                  7'b10_0x1x_0 : acc_step = acc_ok;     //                      WRITE Adr. is not perfect and waits for last packet
                  7'b10_01xx_0 : acc_step = acc_ok;     //                      WRITE Adr. perfect - acc_step after 1. packet
                  7'b10_0100_0 : acc_step = acc_ok;     //                      WRITE Adr. perfect - acc_step after 1. packet if not io_acc
                // fast QWord READ : there would be a 2. acc_step if not ~PACK... 
                // fast QWord READ : there would be a 2. acc_step if not ~PACK... 
                  7'b11_1xxx_x : acc_step = acc_ok & ( (qwa_flag & ~io_rdy & ca_hit) ? ~PACKET[3] : PACKET[3] );
                  7'b11_1xxx_x : acc_step = acc_ok & ( (qwa_flag & ~io_rdy & ca_hit) ? ~PACKET[3] : PACKET[3] );
                  7'b11_0x1x_x : acc_step = acc_ok;
                  7'b11_0x1x_x : acc_step = acc_ok;
                  7'b11_0100_x : acc_step = acc_ok;     //                      WRITE Adr. perfect - acc_step after 1. packet if not io_acc
                  7'b11_0100_x : acc_step = acc_ok;     //                      WRITE Adr. perfect - acc_step after 1. packet if not io_acc
                  default      : acc_step = 1'b0;
                  default      : acc_step = 1'b0;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.