| Line 2... |
Line 2... |
//
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//
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// This file is part of the M32632 project
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// This file is part of the M32632 project
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// http://opencores.org/project,m32632
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// http://opencores.org/project,m32632
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//
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//
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// Filename: ADDR_UNIT.v
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// Filename: ADDR_UNIT.v
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// Version: 1.1 bug fix
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// Version: 1.2 bug fix
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// History: 1.0 first release of 30 Mai 2015
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// History: 1.1 bug fix release of 7 October 2015
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// Date: 7 October 2015
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// 1.0 first release of 30 Mai 2015
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// Date: 8 March 2016
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//
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//
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// Copyright (C) 2015 Udo Moeller
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// Copyright (C) 2015 Udo Moeller
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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| Line 156... |
Line 157... |
default : sign_ext_src1 = SRC1;
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default : sign_ext_src1 = SRC1;
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endcase
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endcase
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always @(index_sel or sign_ext_src1 or SRC1)
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always @(index_sel or sign_ext_src1 or SRC1)
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casex (index_sel)
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casex (index_sel)
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4'b1_0xx : index_val = sign_ext_src1; // für CASE
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4'b1_0xx : index_val = sign_ext_src1; // f�r CASE
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4'b1_1xx : index_val = {{ 3{sign_ext_src1[31]}},sign_ext_src1[31:3]}; // for Bit Opcodes
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4'b1_1xx : index_val = {{ 3{sign_ext_src1[31]}},sign_ext_src1[31:3]}; // for Bit Opcodes
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4'b0_100 : index_val = SRC1;
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4'b0_100 : index_val = SRC1;
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4'b0_101 : index_val = {SRC1[30:0],1'b0};
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4'b0_101 : index_val = {SRC1[30:0],1'b0};
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4'b0_110 : index_val = {SRC1[29:0],2'b00};
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4'b0_110 : index_val = {SRC1[29:0],2'b00};
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4'b0_111 : index_val = {SRC1[28:0],3'b000};
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4'b0_111 : index_val = {SRC1[28:0],3'b000};
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| Line 317... |
Line 318... |
casex ({SIZE,READ_OUT,frueh_ok,PACKET[3],io_acc,all_ok})
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casex ({SIZE,READ_OUT,frueh_ok,PACKET[3],io_acc,all_ok})
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7'b00_xxxx_x : acc_step = acc_ok; // Byte, all ok
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7'b00_xxxx_x : acc_step = acc_ok; // Byte, all ok
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//
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//
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7'b01_xxxx_1 : acc_step = acc_ok; // Word : aligned access , only 1 packet
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7'b01_xxxx_1 : acc_step = acc_ok; // Word : aligned access , only 1 packet
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7'b01_1x1x_0 : acc_step = acc_ok; // READ must wait for all data
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7'b01_1x1x_0 : acc_step = acc_ok; // READ must wait for all data
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7'b01_001x_0 : acc_step = acc_ok; // WRITE Adr. ist not perfect and waits for last packet
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7'b01_0x1x_0 : acc_step = acc_ok; // WRITE Adr. is not perfect and waits for last packet
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7'b01_01xx_0 : acc_step = acc_ok; // WRITE Adr. perfect - acc_step after 1. packet
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7'b01_0100_0 : acc_step = acc_ok; // WRITE Adr. perfect - acc_step after 1. packet if not io_acc
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//
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//
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7'b10_xxxx_1 : acc_step = acc_ok; // DWord : aligned access , only 1 packet
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7'b10_xxxx_1 : acc_step = acc_ok; // DWord : aligned access , only 1 packet
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7'b10_1x1x_0 : acc_step = acc_ok; // READ must wait for all data
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7'b10_1x1x_0 : acc_step = acc_ok; // READ must wait for all data
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7'b10_001x_0 : acc_step = acc_ok; // WRITE Adr. ist not perfect and waits for last packet
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7'b10_0x1x_0 : acc_step = acc_ok; // WRITE Adr. is not perfect and waits for last packet
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7'b10_01xx_0 : acc_step = acc_ok; // WRITE Adr. perfect - acc_step after 1. packet
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7'b10_0100_0 : acc_step = acc_ok; // WRITE Adr. perfect - acc_step after 1. packet if not io_acc
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// fast QWord READ : there would be a 2. acc_step if not ~PACK...
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// fast QWord READ : there would be a 2. acc_step if not ~PACK...
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7'b11_1xxx_x : acc_step = acc_ok & ( (qwa_flag & ~io_rdy & ca_hit) ? ~PACKET[3] : PACKET[3] );
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7'b11_1xxx_x : acc_step = acc_ok & ( (qwa_flag & ~io_rdy & ca_hit) ? ~PACKET[3] : PACKET[3] );
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7'b11_0x1x_x : acc_step = acc_ok;
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7'b11_0x1x_x : acc_step = acc_ok;
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7'b11_0100_x : acc_step = acc_ok; // WRITE Adr. perfect - acc_step after 1. packet if not io_acc
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7'b11_0100_x : acc_step = acc_ok; // WRITE Adr. perfect - acc_step after 1. packet if not io_acc
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default : acc_step = 1'b0;
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default : acc_step = 1'b0;
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