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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
//
// This file is part of the M32632 project
// This file is part of the M32632 project
// http://opencores.org/project,m32632
// http://opencores.org/project,m32632
//
//
//      Filename:       ADDR_UNIT.v
//      Filename:       ADDR_UNIT.v
//      Version:        2.0
//      Version:        3.0
//      History:        1.1 bug fix of 7 October 2015
//      History:        2.0 of 11 August 2016
 
//                              1.1 bug fix of 7 October 2015
//                              1.0 first release of 30 Mai 2015
//                              1.0 first release of 30 Mai 2015
//      Date:           14 August 2016
//      Date:           2 December 2018
//
//
// Copyright (C) 2016 Udo Moeller
// Copyright (C) 2018 Udo Moeller
// 
// 
// This source file may be used and distributed without 
// This source file may be used and distributed without 
// restriction provided that this copyright statement is not 
// restriction provided that this copyright statement is not 
// removed from the file and that any derivative work contains 
// removed from the file and that any derivative work contains 
// the original copyright notice and the associated disclaimer.
// the original copyright notice and the associated disclaimer.
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// 
// 
// You should have received a copy of the GNU Lesser General 
// You should have received a copy of the GNU Lesser General 
// Public License along with this source; if not, download it 
// Public License along with this source; if not, download it 
// from http://www.opencores.org/lgpl.shtml 
// from http://www.opencores.org/lgpl.shtml 
// 
// 
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
//
//      Modules contained in this file:
//      Modules contained in this file:
//      ADDR_UNIT       generates data access addresses and controls data cache operation
//      ADDR_UNIT       generates data access addresses and controls data cache operation
//
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 
 
module ADDR_UNIT ( BCLK, BRESET, READ, WRITE, LDEA, NEWACC, CLRMSW, POST, DISP_OK, FULLACC, SRC2SEL, INDEX, ASIZE, SRC1, SRC2, BWD,
module ADDR_UNIT ( BCLK, BRESET, READ, WRITE, LDEA, NEWACC, CLRMSW, POST, DISP_OK, FULLACC, SRC2SEL, INDEX, ASIZE, SRC1, SRC2, BWD,
                                   DISP, PC_ARCHI, PC_ICACHE, IO_READY, ACC_STAT, MMU_UPDATE, IC_TEX, ABO_STAT, ADIVAR, RWVAL_1, OP_RMW, PHASE_17,
                                   DISP, PC_ARCHI, PC_ICACHE, IO_READY, ACC_STAT, MMU_UPDATE, IC_TEX, ABO_STAT, ADIVAR, RWVAL_1, OP_RMW, PHASE_17,
                                   NO_TRAP, FPU_TRAP, READ_OUT, WRITE_OUT, ZTEST, RMW, VADR, ADDR, SIZE, PACKET, ACC_DONE, ABORT, REG_OUT, BITSEL,
                                   NO_TRAP, FPU_TRAP, READ_OUT, WRITE_OUT, ZTEST, RMW, VADR, ADDR, SIZE, PACKET, ACC_DONE, ABORT, CTRL_QW, BITSEL,
                                   QWATWO );
                                   QWATWO );
 
 
        input                   BCLK,BRESET;
        input                   BCLK,BRESET;
        input                   READ,WRITE,LDEA;
        input                   READ,WRITE,LDEA;
        input                   NEWACC;
        input                   NEWACC;
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        output  [31:0]   ADDR;
        output  [31:0]   ADDR;
        output   [1:0]   SIZE;
        output   [1:0]   SIZE;
        output   [3:0]   PACKET;
        output   [3:0]   PACKET;
        output                  ACC_DONE;
        output                  ACC_DONE;
        output                  ABORT;
        output                  ABORT;
        output                  REG_OUT;
        output   [1:0]   CTRL_QW;
        output   [2:0]   BITSEL;
        output   [2:0]   BITSEL;
        output  reg             QWATWO;
        output  reg             QWATWO;
 
 
        reg             [31:0]   VADR;
        reg             [31:0]   VADR;
        reg                             READ_OUT,write_reg,ZTEST,RMW;
        reg                             READ_OUT,write_reg,ZTEST,RMW;
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        reg                             ABORT;
        reg                             ABORT;
        reg              [1:0]   tex_feld;
        reg              [1:0]   tex_feld;
        reg              [2:0]   u_ddt;
        reg              [2:0]   u_ddt;
        reg                             pg_op;
        reg                             pg_op;
        reg                             do_wr;
        reg                             do_wr;
 
        reg                             irdy_flag;
 
 
        wire                    acc_ok,acc_err,io_acc;
        wire                    acc_ok,acc_err,io_acc;
        wire                    acc_pass;
        wire                    acc_pass;
        wire                    ca_hit;
        wire                    ca_hit;
        wire    [31:0]   reg_adder;
        wire    [31:0]   reg_adder;
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                  default : sign_ext_src1 = SRC1;
                  default : sign_ext_src1 = SRC1;
                endcase
                endcase
 
 
        always @(index_sel or sign_ext_src1 or SRC1)
        always @(index_sel or sign_ext_src1 or SRC1)
                casex (index_sel)
                casex (index_sel)
                  4'b1_0xx : index_val = sign_ext_src1; // für CASE
                  4'b1_0xx : index_val = sign_ext_src1; // f�r CASE
                  4'b1_1xx : index_val = {{ 3{sign_ext_src1[31]}},sign_ext_src1[31:3]}; // for Bit Opcodes
                  4'b1_1xx : index_val = {{ 3{sign_ext_src1[31]}},sign_ext_src1[31:3]}; // for Bit Opcodes
                  4'b0_100 : index_val = SRC1;
                  4'b0_100 : index_val = SRC1;
                  4'b0_101 : index_val = {SRC1[30:0],1'b0};
                  4'b0_101 : index_val = {SRC1[30:0],1'b0};
                  4'b0_110 : index_val = {SRC1[29:0],2'b00};
                  4'b0_110 : index_val = {SRC1[29:0],2'b00};
                  4'b0_111 : index_val = {SRC1[28:0],3'b000};
                  4'b0_111 : index_val = {SRC1[28:0],3'b000};
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        assign ACC_DONE = acc_run ? (acc_step & ~no_done) : ea_ok;
        assign ACC_DONE = acc_run ? (acc_step & ~no_done) : ea_ok;
 
 
        // Bugfix of 7.October 2015
        // Bugfix of 7.October 2015
        always @(posedge BCLK) QWATWO <= acc_run & acc_ok & qwa_flag & ~io_rdy & ca_hit & ~PACKET[3] & (SIZE == 2'b11) & READ_OUT & ~no_done;
        always @(posedge BCLK) QWATWO <= acc_run & acc_ok & qwa_flag & ~io_rdy & ca_hit & ~PACKET[3] & (SIZE == 2'b11) & READ_OUT & ~no_done;
 
 
        always @(posedge BCLK) reg_out_i <= ~acc_step & BRESET & ((qwa_flag & (io_rdy | ~ca_hit) & acc_ok) | reg_out_i);
        always @(posedge BCLK) reg_out_i <= ~acc_step & BRESET & ((qwa_flag & ~io_rdy & ~ca_hit & acc_ok) | reg_out_i);
 
 
        always @(posedge BCLK) io_rdy  <= IO_READY & (WRITE_OUT | READ_OUT);
        always @(posedge BCLK) irdy_flag <= (READ_OUT & io_acc) | (irdy_flag & ~IO_READY);      // new 25.6.2018
 
        always @(posedge BCLK) io_rdy  <= IO_READY & irdy_flag;
 
 
        always @(posedge BCLK) next_reg <= (acc_step & ~qwa_flag) & (SIZE == 2'b11);
        always @(posedge BCLK) next_reg <= acc_step & (qwa_flag ? io_rdy : 1'b1) & (SIZE == 2'b11);
        assign REG_OUT = reg_out_i | next_reg;
        assign CTRL_QW = {qwa_flag,(reg_out_i | next_reg)};
 
 
endmodule
endmodule
 
 
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