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Line 34... |
//
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//
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// Modules contained in this file:
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// Modules contained in this file:
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// 1. WR_ALINGER alignes write data to cache and external devices
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// 1. WR_ALINGER alignes write data to cache and external devices
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// 2. RD_ALINGER alignes read data for the data path
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// 2. RD_ALINGER alignes read data for the data path
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//
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//
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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|
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// 1. WR_ALINGER alignes write data to cache and external devices
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// 1. WR_ALINGER alignes write data to cache and external devices
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//
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//
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module WR_ALIGNER ( PACKET, DP_Q, SIZE, WRDATA, ENBYTE );
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module WR_ALIGNER ( PACKET, DP_Q, SIZE, WRDATA, ENBYTE );
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input [3:0] PACKET; // [3:2] Paketnumber , [1:0] Startaddress
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input [3:0] PACKET; // [3:2] Paketnumber , [1:0] Startaddress
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input [63:0] DP_Q;
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input [63:0] DP_Q;
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input [1:0] SIZE;
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input [1:0] SIZE;
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| Line 165... |
Line 165... |
6'b10_1x_11 : ENBYTE = 4'b0111;
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6'b10_1x_11 : ENBYTE = 4'b0111;
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endcase
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endcase
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endmodule
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endmodule
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// 2. RD_ALINGER alignes read data for the data path
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// 2. RD_ALINGER alignes read data for the data path
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//
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//
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module RD_ALIGNER ( BCLK, ACC_OK, PACKET, SIZE, REG_OUT, RDDATA, CA_HIT, DP_DI, AUX_QW );
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module RD_ALIGNER ( BCLK, ACC_OK, PACKET, SIZE, REG_OUT, RDDATA, CA_HIT, DP_DI, AUX_QW );
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input BCLK;
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input BCLK;
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input ACC_OK;
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input ACC_OK;
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input [3:0] PACKET; // [3:2] Paketnumber , [1:0] Startaddress
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input [3:0] PACKET; // [3:2] Paketnumber , [1:0] Startaddress
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| Line 194... |
Line 194... |
// Not aligned QWORD : ADR[1:0] = 3 i.e.
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// Not aligned QWORD : ADR[1:0] = 3 i.e.
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// Bytes to datapath : . - . - 4 - 4
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// Bytes to datapath : . - . - 4 - 4
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// Bytes from memory : 1 - 4 - 3 - .
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// Bytes from memory : 1 - 4 - 3 - .
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// ACC_DONE : _______/----\__
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// ACC_DONE : _______/----\__
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// + 1 cycle ____/--
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// + 1 cycle ____/--
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// at the end 2 cycles lost. ACC_DONE informs the Op-Dec that data is available and sent one clock c
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// at the end 2 cycles lost. ACC_DONE informs the Op-Dec that data is available and sent one clock cycle later
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// the LSD of QWORD access. (ACC_DONE -> REG_OUT is happening in ADDR_UNIT.)
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// the LSD of QWORD access. (ACC_DONE -> REG_OUT is happening in ADDR_UNIT.)
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//
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//
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// SIZE PACKET ADR : Output data ACC_OK
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// SIZE PACKET ADR : Output data ACC_OK
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// 00 -- 00 x x x B0 Byte 1
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// 00 -- 00 x x x B0 Byte 1
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// 00 -- 01 x x x B1 1
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// 00 -- 01 x x x B1 1
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