| Line 2... |
Line 2... |
//
|
//
|
// This file is part of the M32632 project
|
// This file is part of the M32632 project
|
// http://opencores.org/project,m32632
|
// http://opencores.org/project,m32632
|
//
|
//
|
// Filename: CACHE_LOGIK.v
|
// Filename: CACHE_LOGIK.v
|
// Version: 1.0
|
// Version: 1.1 bug fix
|
// Date: 30 May 2015
|
// History: 1.0 first release of 30 Mai 2015
|
|
// Date: 7 October 2015
|
//
|
//
|
// Copyright (C) 2015 Udo Moeller
|
// Copyright (C) 2015 Udo Moeller
|
//
|
//
|
// This source file may be used and distributed without
|
// This source file may be used and distributed without
|
// restriction provided that this copyright statement is not
|
// restriction provided that this copyright statement is not
|
| Line 407... |
Line 408... |
// 6. DCACHE_SM Data cache state machine
|
// 6. DCACHE_SM Data cache state machine
|
//
|
//
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
module DCACHE_SM ( BCLK, BRESET, IO_SPACE, MDONE, IO_READY, MMU_HIT, CA_HIT, READ, WRITE, ZTEST, RMW, CAPDAT, VADR_R, IC_VA,
|
module DCACHE_SM ( BCLK, BRESET, IO_SPACE, MDONE, IO_READY, MMU_HIT, CA_HIT, READ, WRITE, ZTEST, RMW, CAPDAT, VADR_R, IC_VA,
|
USE_CA, PTB_WR, PTB_SEL, SEL_PTB1, CPU_OUT, USER, PROT_ERROR, WB_ACC, ENWR, ADR_EQU, IC_PREQ, FILLRAM, ICTODC,
|
USE_CA, PTB_WR, PTB_SEL, SEL_PTB1, CPU_OUT, USER, PROT_ERROR, WB_ACC, ENWR, ADR_EQU, IC_PREQ, FILLRAM, ICTODC,
|
RWVAL, VIRTUELL,
|
RWVAL, VIRTUELL, QWATWO,
|
DRAM_ACC, DRAM_WR, IO_ACC, IO_RD, IO_WR, PTE_MUX, PD_MUX, PKEEP, PTE_ADR, PTE_DAT, HIT_ALL, ACC_OK,
|
DRAM_ACC, DRAM_WR, IO_ACC, IO_RD, IO_WR, PTE_MUX, PD_MUX, PKEEP, PTE_ADR, PTE_DAT, HIT_ALL, ACC_OK,
|
ABORT, PROTECT, IACC_STAT, ABO_LEVEL1, WR_MRAM, CUPDATE, AUX_DAT, NEW_PTB, PTB_ONE, MMU_DIN, IC_SIGS, KOMUX,
|
ABORT, PROTECT, IACC_STAT, ABO_LEVEL1, WR_MRAM, CUPDATE, AUX_DAT, NEW_PTB, PTB_ONE, MMU_DIN, IC_SIGS, KOMUX,
|
KDET, DMA_MUX, HLDA, RWVFLAG, PTE_STAT );
|
KDET, DMA_MUX, HLDA, RWVFLAG, PTE_STAT );
|
|
|
input BCLK;
|
input BCLK;
|
| Line 435... |
Line 436... |
input IC_PREQ;
|
input IC_PREQ;
|
input FILLRAM;
|
input FILLRAM;
|
input [3:0] ICTODC; // multiple signals from ICACHE, especially DMA
|
input [3:0] ICTODC; // multiple signals from ICACHE, especially DMA
|
input [1:0] RWVAL; // RDVAL+WRVAL Operation
|
input [1:0] RWVAL; // RDVAL+WRVAL Operation
|
input VIRTUELL; // for RDVAL/WRVAL
|
input VIRTUELL; // for RDVAL/WRVAL
|
|
input QWATWO;
|
|
|
output reg DRAM_ACC,DRAM_WR;
|
output reg DRAM_ACC,DRAM_WR;
|
output IO_ACC,IO_RD,IO_WR;
|
output IO_ACC,IO_RD,IO_WR;
|
output PTE_MUX,PD_MUX,PKEEP;
|
output PTE_MUX,PD_MUX,PKEEP;
|
output [27:0] PTE_ADR;
|
output [27:0] PTE_ADR;
|
| Line 664... |
Line 666... |
default : ko_state <= 3'b000;
|
default : ko_state <= 3'b000;
|
endcase
|
endcase
|
|
|
assign kostart = pte_go | rd_level2;
|
assign kostart = pte_go | rd_level2;
|
|
|
assign run_dc = ~ko_state[2] & ~dma_run;
|
// ko_state[2] suppresses ACC_OK at READ
|
|
assign run_dc = (~ko_state[2] | QWATWO) & ~dma_run; // Bugfix of 7.10.2015
|
assign KOMUX = ko_state[1] | DMA_MUX;
|
assign KOMUX = ko_state[1] | DMA_MUX;
|
assign KDET = ko_state[0] | dma_kdet;
|
assign KDET = ko_state[0] | dma_kdet;
|
|
|
assign HIT_ALL = MMU_HIT & CA_HIT & run_dc & ~pte_acc; // for Update "Last-Set" , MMU_HIT contains ZUGRIFF
|
assign HIT_ALL = MMU_HIT & CA_HIT & run_dc & ~pte_acc; // for Update "Last-Set" , MMU_HIT contains ZUGRIFF
|
|
|
