| Line 2... |
Line 2... |
//
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//
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// This file is part of the M32632 project
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// This file is part of the M32632 project
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// http://opencores.org/project,m32632
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// http://opencores.org/project,m32632
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//
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//
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// Filename: CACHE_LOGIK.v
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// Filename: CACHE_LOGIK.v
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// Version: 1.1 bug fix
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// Version: 2.0
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// History: 1.0 first release of 30 Mai 2015
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// History: 1.1 bug fix of 7 October 2015
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// Date: 7 October 2015
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// 1.0 first release of 30 Mai 2015
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// Date: 14 August 2016
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//
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//
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// Copyright (C) 2015 Udo Moeller
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// Copyright (C) 2016 Udo Moeller
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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| Line 32... |
Line 33... |
// from http://www.opencores.org/lgpl.shtml
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// from http://www.opencores.org/lgpl.shtml
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//
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//
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// Modules contained in this file:
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// Modules contained in this file:
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// 1. DEBUG_AE Debug unit for address compare in data cache
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// 1. NEU_VALID Cache Valid RAM
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// 2. MMU_UP MMU memory update and initalization controller
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// 2. DEBUG_AE Debug unit for address compare in data cache
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// 3. DCA_CONTROL Data cache valid memory update and initalization controller
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// 3. MMU_UP MMU memory update and initalization controller
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// 4. MMU_MATCH MMU virtual address match detector
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// 4. DCA_CONTROL Data cache valid memory update and initalization controller
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// 5. CA_MATCH Cache tag match detector
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// 5. MMU_MATCH MMU virtual address match detector
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// 6. DCACHE_SM Data cache state machine
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// 6. CA_MATCH Cache tag match detector
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// 7. FILTCMP Address Filter and Comparator
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// 8. DCACHE_SM Data cache state machine
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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|
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// 1. DEBUG_AE Debug unit for address compare in data cache
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// 1. NEU_VALID Cache Valid RAM
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module NEU_VALID ( BCLK, VALIN, WADR, WREN, RADR, VALOUT );
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input BCLK;
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input [23:0] VALIN;
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input [4:0] WADR;
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input WREN;
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input [4:0] RADR;
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output [23:0] VALOUT;
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reg [23:0] cvalid [0:31]; // Valid bits for Data Set 0 and 1 : 32 entries of 24 bits
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reg [23:0] ramout;
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reg [23:0] valhold;
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reg gleich;
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always @(posedge BCLK) ramout <= cvalid[RADR];
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always @(posedge BCLK) if (WREN) cvalid[WADR] <= VALIN;
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always @(posedge BCLK) valhold <= VALIN;
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always @(posedge BCLK) gleich <= WREN & (RADR == WADR);
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assign VALOUT = gleich ? valhold : ramout;
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endmodule
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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// 2. DEBUG_AE Debug unit for address compare in data cache
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module DEBUG_AE ( DBG_IN, READ, WRITE, USER, VIRTUELL, ACC_OK, VADR_R, MMU_Q, ENBYTE, DBG_HIT );
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module DEBUG_AE ( DBG_IN, READ, WRITE, USER, VIRTUELL, ACC_OK, VADR_R, MMU_Q, ENBYTE, DBG_HIT );
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input [40:2] DBG_IN;
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input [40:2] DBG_IN;
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| Line 90... |
Line 123... |
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endmodule
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endmodule
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// 2. MMU_UP MMU memory update and initalization controller
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// 3. MMU_UP MMU memory update and initalization controller
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module MMU_UP ( BCLK, BRESET, NEW_PTB, PTB1, IVAR, WR_MRAM, VADR, VADR_R, MVALID, UPDATE,
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module MMU_UP ( BCLK, BRESET, NEW_PTB, PTB1, IVAR, WR_MRAM, VADR, VADR_R, MVALID, UPDATE,
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WE_MV, WADR_MV, RADR_MV, DAT_MV, NEW_PTB_RUN );
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WE_MV, WADR_MV, RADR_MV, DAT_MV, NEW_PTB_RUN );
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| Line 141... |
Line 174... |
|
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endmodule
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endmodule
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// 3. DCA_CONTROL Data cache valid memory update and initalization controller
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// 4. DCA_CONTROL Data cache valid memory update and initalization controller
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module DCA_CONTROL ( BCLK, MCLK, BRESET, CUPDATE, DRAM_ACC, CA_SET, HIT_ALL, WRCFG, VADR_R, UPDATE, INVAL_A, WRITE,
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module DCA_CONTROL ( BCLK, MCLK, BRESET, CUPDATE, DRAM_ACC, CA_SET, HIT_ALL, WRCFG, VADR_R, UPDATE, INVAL_A, WRITE,
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WCTRL, KILL, WRCRAM0, WRCRAM1, WE_CV, WADR_CV, DAT_CV, INIT_CA_RUN, WRSET0, WRSET1 );
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WCTRL, KILL, WRCRAM0, WRCRAM1, WE_CV, WADR_CV, DAT_CV, INIT_CA_RUN, WRSET0, WRSET1 );
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| Line 178... |
Line 211... |
reg dly_bclk,zero,wr_puls;
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reg dly_bclk,zero,wr_puls;
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reg [2:0] count,refer;
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reg [2:0] count,refer;
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|
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wire countf;
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wire countf;
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always @(posedge BCLK) if (DRAM_ACC) ca_set_d <= CA_SET; // Store for whole access
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// physical address is stored in TAG-RAM
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// physical address is stored in TAG-RAM
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assign WRCRAM0 = (CUPDATE & ~WCTRL[0]) & ~CA_SET;
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assign WRCRAM0 = (CUPDATE & ~WCTRL[0]) & ~ca_set_d;
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assign WRCRAM1 = (CUPDATE & ~WCTRL[0]) & CA_SET;
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assign WRCRAM1 = (CUPDATE & ~WCTRL[0]) & ca_set_d;
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// Load Valid RAM :
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// Load Valid RAM :
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|
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assign WE_CV = state[1] | HIT_ALL | (CUPDATE & ~WCTRL[0]) | KILL; // Hit All for "Last" Update
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assign WE_CV = state[1] | HIT_ALL | (CUPDATE & ~WCTRL[0]) | KILL; // Hit All for "Last" Update
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assign WADR_CV = state[1] ? acount : VADR_R;
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assign WADR_CV = state[1] ? acount : VADR_R;
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| Line 208... |
Line 243... |
|
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always @(posedge BCLK) if (!state[1]) acount <= 5'h0; else acount <= acount + 5'h01;
|
always @(posedge BCLK) if (!state[1]) acount <= 5'h0; else acount <= acount + 5'h01;
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|
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assign INIT_CA_RUN = state[1];
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assign INIT_CA_RUN = state[1];
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|
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always @(posedge BCLK) if (DRAM_ACC) ca_set_d <= CA_SET;
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|
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// WRITE Control in data RAMs
|
// WRITE Control in data RAMs
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assign WRSET0 = ( ~CA_SET & WRITE & HIT_ALL & wr_puls) | (WCTRL[1] & ~ca_set_d);
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assign WRSET0 = ( ~CA_SET & WRITE & HIT_ALL & wr_puls) | (WCTRL[1] & ~ca_set_d);
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assign WRSET1 = ( CA_SET & WRITE & HIT_ALL & wr_puls) | (WCTRL[1] & ca_set_d);
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assign WRSET1 = ( CA_SET & WRITE & HIT_ALL & wr_puls) | (WCTRL[1] & ca_set_d);
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|
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// ++++++++++++ Special circuit for Timing of write pulse for data RAM of data cache +++++++++
|
// ++++++++++++ Special circuit for Timing of write pulse for data RAM of data cache +++++++++
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| Line 235... |
Line 268... |
|
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endmodule
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endmodule
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|
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// 4. MMU_MATCH MMU virtual address match detector
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// 5. MMU_MATCH MMU virtual address match detector
|
//
|
//
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module MMU_MATCH ( USER, READ, WRITE, RMW, MCR_FLAGS, MVALID, VADR_R, MMU_VA, IVAR,
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module MMU_MATCH ( USER, READ, WRITE, RMW, MCR_FLAGS, MVALID, VADR_R, MMU_VA, IVAR,
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VIRTUELL, MMU_HIT , UPDATE, PROT_ERROR, CI, SEL_PTB1 );
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VIRTUELL, MMU_HIT , UPDATE, PROT_ERROR, CI, SEL_PTB1 );
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| Line 296... |
Line 329... |
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assign match = (VADR_R[31:20] == MMU_VA[31:20]) & (adr_space == as_sorte) & ((MVALID[15:0] & maske) != 16'h0000);
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assign match = (VADR_R[31:20] == MMU_VA[31:20]) & (adr_space == as_sorte) & ((MVALID[15:0] & maske) != 16'h0000);
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assign alles_ok = match & ( ~WRITE | MMU_VA[17] ) & ~PROT_ERROR; // Modified - Flag : reload the PTE
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assign alles_ok = match & ( ~WRITE | MMU_VA[17] ) & ~PROT_ERROR; // Modified - Flag : reload the PTE
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// if MMU_HIT = 0 then there is no Write-Buffer access abd no update of cache !
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// if MMU_HIT = 0 then there is no Write-Buffer access and no update of cache !
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assign MMU_HIT = zugriff ? ( VIRTUELL ? alles_ok : 1'b1 ) : 1'b0 ; // MMU off : then always HIT
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assign MMU_HIT = zugriff ? ( VIRTUELL ? alles_ok : 1'b1 ) : 1'b0 ; // MMU off : then always HIT
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assign val_bits = IVAR[1] ? (MVALID[15:0] & (match ? ~maske : 16'hFFFF)) : (MVALID[15:0] | maske);
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assign val_bits = IVAR[1] ? (MVALID[15:0] & (match ? ~maske : 16'hFFFF)) : (MVALID[15:0] | maske);
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assign as_bits = IVAR[1] ? MVALID[31:16] : (adr_space ? (MVALID[31:16] | maske) : (MVALID[31:16] & ~maske));
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assign as_bits = IVAR[1] ? MVALID[31:16] : (adr_space ? (MVALID[31:16] | maske) : (MVALID[31:16] & ~maske));
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| Line 322... |
Line 355... |
|
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endmodule
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endmodule
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|
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// 5. CA_MATCH Cache tag match detector
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// 6. CA_MATCH Cache tag match detector
|
//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module CA_MATCH ( CVALID, IOSEL, ADDR, TAG0, TAG1, CFG, WRITE, MMU_HIT, CI, INVAL_L, KDET, ENDRAM, DC_ILO,
|
module CA_MATCH ( CVALID, DRAMSZ, ADDR, TAG0, TAG1, CFG, WRITE, MMU_HIT, CI, INVAL_L, KDET, ENDRAM, DC_ILO,
|
CA_HIT, CA_SET, UPDATE, IO_SPACE, USE_CA, WB_ACC, KILL );
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CA_HIT, CA_SET, UPDATE, IO_SPACE, USE_CA, WB_ACC, KILL );
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input [23:0] CVALID;
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input [23:0] CVALID;
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input [3:0] IOSEL;
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input [2:0] DRAMSZ;
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input [27:4] ADDR;
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input [31:4] ADDR;
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input [27:12] TAG0,TAG1;
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input [27:12] TAG0,TAG1;
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input [1:0] CFG; // LDC , DC
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input [1:0] CFG; // LDC , DC
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input WRITE;
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input WRITE;
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input MMU_HIT;
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input MMU_HIT;
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input CI;
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input CI;
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| Line 350... |
Line 383... |
output USE_CA;
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output USE_CA;
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output WB_ACC;
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output WB_ACC;
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output KILL;
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output KILL;
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reg [7:0] maske;
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reg [7:0] maske;
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reg [4:0] szmaske;
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|
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wire match_0,match_1;
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wire match_0,match_1;
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wire valid_0,valid_1;
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wire valid_0,valid_1;
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wire select;
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wire select;
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wire clear;
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wire clear;
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wire [7:0] update_0,update_1,lastinfo;
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wire [7:0] update_0,update_1,lastinfo;
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wire sel_dram;
|
wire sel_dram,filter;
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|
|
always @(ADDR)
|
always @(ADDR)
|
case (ADDR[6:4])
|
case (ADDR[6:4])
|
3'h0 : maske = 8'h01;
|
3'h0 : maske = 8'h01;
|
3'h1 : maske = 8'h02;
|
3'h1 : maske = 8'h02;
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| Line 394... |
Line 428... |
|
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assign UPDATE = {lastinfo,update_1,update_0};
|
assign UPDATE = {lastinfo,update_1,update_0};
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|
|
assign KILL = clear & CA_HIT & ~CFG[1]; // only if cache is not locked
|
assign KILL = clear & CA_HIT & ~CFG[1]; // only if cache is not locked
|
|
|
assign sel_dram = (IOSEL == 4'b0000) & ENDRAM; // at the moment the first 256 MB of memory
|
always @(DRAMSZ) // Size of DRAM
|
|
casex (DRAMSZ)
|
|
3'b00x : szmaske = 5'h1F; // 8 MB 32016 Second Processor
|
|
// 3'b001 reserved for Ceres III
|
|
3'b01x : szmaske = 5'h10; // 128 MB MCUBE
|
|
default : szmaske = 5'h00; // 256 MB NetBSD
|
|
endcase
|
|
|
|
assign filter = ((ADDR[27:23] & szmaske) == 5'd0);
|
|
assign sel_dram = (ADDR[31:28] == 4'd0) & filter & ENDRAM;
|
assign IO_SPACE = ~sel_dram; // not DRAM or DRAM ist off
|
assign IO_SPACE = ~sel_dram; // not DRAM or DRAM ist off
|
|
|
assign USE_CA = ~CI & ~DC_ILO & CFG[0] & ~CFG[1]; // CI ? ILO ? Cache on ? Locked Cache ?
|
assign USE_CA = ~CI & ~DC_ILO & CFG[0] & ~CFG[1]; // CI ? ILO ? Cache on ? Locked Cache ?
|
assign WB_ACC = WRITE & MMU_HIT & sel_dram;
|
assign WB_ACC = WRITE & MMU_HIT & sel_dram;
|
|
|
endmodule
|
endmodule
|
|
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
//
|
//
|
// 6. DCACHE_SM Data cache state machine
|
// 7. FILTCMP Address Filter and Comparator
|
|
//
|
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
module FILTCMP ( DRAMSZ, RADR, DRAM_A, ADR_EQU, TAGDAT );
|
|
|
|
input [2:0] DRAMSZ;
|
|
input [27:4] RADR,DRAM_A;
|
|
|
|
output ADR_EQU;
|
|
output reg [27:12] TAGDAT;
|
|
|
|
reg [27:23] adram;
|
|
|
|
always @(DRAMSZ or RADR)
|
|
casex (DRAMSZ)
|
|
3'b00x : TAGDAT = {5'd0,RADR[22:12]}; // 8 MB
|
|
3'bx10 : TAGDAT = {3'd0,RADR[24:12]}; // 32 MB
|
|
3'bx11 : TAGDAT = {2'd0,RADR[25:12]}; // 64 MB
|
|
3'b100 : TAGDAT = {1'd0,RADR[26:12]}; // 128 MB
|
|
3'b101 : TAGDAT = RADR[27:12] ; // 256 MB
|
|
endcase
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|
|
|
always @(DRAMSZ or DRAM_A) // The address comparator is only used in the data cache.
|
|
casex (DRAMSZ)
|
|
3'b00x : adram = 5'd0; // 8 MB
|
|
3'bx10 : adram = {3'd0,DRAM_A[24:23]}; // 32 MB
|
|
3'bx11 : adram = {2'd0,DRAM_A[25:23]}; // 64 MB
|
|
3'b100 : adram = {1'd0,DRAM_A[26:23]}; // 128 MB
|
|
3'b101 : adram = DRAM_A[27:23] ; // 256 MB
|
|
endcase
|
|
|
|
assign ADR_EQU = {TAGDAT,RADR[11:4]} == {adram,DRAM_A[22:4]};
|
|
|
|
endmodule
|
|
|
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
//
|
|
// 8. DCACHE_SM Data cache state machine
|
//
|
//
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
module DCACHE_SM ( BCLK, BRESET, IO_SPACE, MDONE, IO_READY, MMU_HIT, CA_HIT, READ, WRITE, ZTEST, RMW, CAPDAT, VADR_R, IC_VA,
|
module DCACHE_SM ( BCLK, BRESET, IO_SPACE, MDONE, IO_READY, MMU_HIT, CA_HIT, READ, WRITE, ZTEST, RMW, CAPDAT, VADR_R, IC_VA,
|
USE_CA, PTB_WR, PTB_SEL, SEL_PTB1, CPU_OUT, USER, PROT_ERROR, WB_ACC, ENWR, ADR_EQU, IC_PREQ, FILLRAM, ICTODC,
|
USE_CA, PTB_WR, PTB_SEL, SEL_PTB1, CPU_OUT, USER, PROT_ERROR, WB_ACC, ENWR, ADR_EQU, IC_PREQ, DMA_CHK, ICTODC,
|
RWVAL, VIRTUELL, QWATWO,
|
RWVAL, VIRTUELL, QWATWO,
|
DRAM_ACC, DRAM_WR, IO_ACC, IO_RD, IO_WR, PTE_MUX, PD_MUX, PKEEP, PTE_ADR, PTE_DAT, HIT_ALL, ACC_OK,
|
DRAM_ACC, DRAM_WR, IO_ACC, IO_RD, IO_WR, PTE_MUX, PD_MUX, PKEEP, PTE_ADR, PTE_DAT, HIT_ALL, ACC_OK,
|
ABORT, PROTECT, IACC_STAT, ABO_LEVEL1, WR_MRAM, CUPDATE, AUX_DAT, NEW_PTB, PTB_ONE, MMU_DIN, IC_SIGS, KOMUX,
|
ABORT, PROTECT, IACC_STAT, ABO_LEVEL1, WR_MRAM, CUPDATE, AUX_DAT, NEW_PTB, PTB_ONE, MMU_DIN, IC_SIGS, KOMUX,
|
KDET, DMA_MUX, HLDA, RWVFLAG, PTE_STAT );
|
KDET, DMA_MUX, HLDA, RWVFLAG, PTE_STAT );
|
|
|
| Line 432... |
Line 513... |
input PROT_ERROR;
|
input PROT_ERROR;
|
input WB_ACC;
|
input WB_ACC;
|
input ENWR; // Enable WRITE from DRAM
|
input ENWR; // Enable WRITE from DRAM
|
input ADR_EQU;
|
input ADR_EQU;
|
input IC_PREQ;
|
input IC_PREQ;
|
input FILLRAM;
|
input DMA_CHK;
|
input [3:0] ICTODC; // multiple signals from ICACHE, especially DMA
|
input [3:0] ICTODC; // multiple signals from ICACHE, especially DMA
|
input [1:0] RWVAL; // RDVAL+WRVAL Operation
|
input [1:0] RWVAL; // RDVAL+WRVAL Operation
|
input VIRTUELL; // for RDVAL/WRVAL
|
input VIRTUELL; // for RDVAL/WRVAL
|
input QWATWO;
|
input QWATWO;
|
|
|
| Line 551... |
Line 632... |
// DRAM access : Cache Miss at READ :
|
// DRAM access : Cache Miss at READ :
|
13'b10_0x_1100_00_x_x0 : new_state = 7'b0010010;
|
13'b10_0x_1100_00_x_x0 : new_state = 7'b0010010;
|
// DRAM access : WRITE
|
// DRAM access : WRITE
|
13'b10_0x_101x_x0_x_x0 : new_state = 7'b0000100;
|
13'b10_0x_101x_x0_x_x0 : new_state = 7'b0000100;
|
// PTE Request ICACHE , IO access with WRITE is stored - parallel DRAM access possible
|
// PTE Request ICACHE , IO access with WRITE is stored - parallel DRAM access possible
|
13'b0x_xx_xxxx_x0_1_00 : new_state = 7'b0101010; // no access
|
13'b0x_xx_xxxx_x0_1_x0 : new_state = 7'b0101010; // no access
|
13'b10_0x_1101_x0_1_x0 : new_state = 7'b0101010; // if successful READ a PTE access can happen in parallel
|
13'b10_0x_1101_x0_1_x0 : new_state = 7'b0101010; // if successful READ a PTE access can happen in parallel
|
// DMA access. Attention : no IO-Write access in background and no ICACHE PTE access !
|
// DMA access. Attention : no IO-Write access in background and no ICACHE PTE access !
|
13'b0x_x0_xxxx_xx_0_10 : new_state = 7'b1000000; // DMA access is started
|
13'b0x_x0_xxxx_x0_0_10 : new_state = 7'b1000000; // DMA access is started
|
default : new_state = 7'b0;
|
default : new_state = 7'b0;
|
endcase
|
endcase
|
|
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assign IO_ACC = new_state[0]; // to load registers for data, addr und BE, signal one pulse
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assign IO_ACC = new_state[0]; // to load registers for data, addr und BE, signal one pulse
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assign dram_go = new_state[1] | rd_level2 ;
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assign dram_go = new_state[1] | rd_level2 ;
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| Line 708... |
Line 789... |
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always @(posedge BCLK) dma_run <= (dma_go | (dma_run & dma)) & BRESET; // stops the data access until HOLD becomes inactive
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always @(posedge BCLK) dma_run <= (dma_go | (dma_run & dma)) & BRESET; // stops the data access until HOLD becomes inactive
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assign HLDA = ~(ICTODC[1] & dma_run); // Signal for system that the CPU has stopped accesses
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assign HLDA = ~(ICTODC[1] & dma_run); // Signal for system that the CPU has stopped accesses
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always @(posedge BCLK) dma_kdet <= FILLRAM;
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always @(posedge BCLK) dma_kdet <= DMA_CHK;
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assign DMA_MUX = FILLRAM | dma_kdet;
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assign DMA_MUX = DMA_CHK | dma_kdet;
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// global feedback to ADDR_UNIT, early feedback to Op-Dec : you can continue
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// global feedback to ADDR_UNIT, early feedback to Op-Dec : you can continue
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assign ACC_OK = ZTEST ? (~VIRTUELL | zt_ok)
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assign ACC_OK = ZTEST ? (~VIRTUELL | zt_ok)
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: (IO_SPACE ? ((IO_ACC & WRITE) | rd_done) : (wr_dram | (READ & MMU_HIT & rd_ende & run_dc)) );
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: (IO_SPACE ? ((IO_ACC & WRITE) | rd_done) : (wr_dram | (READ & MMU_HIT & rd_ende & run_dc)) );
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