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//
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//
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// This file is part of the M32632 project
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// This file is part of the M32632 project
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// http://opencores.org/project,m32632
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// http://opencores.org/project,m32632
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//
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//
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// Filename: DATENPFAD.v
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// Filename: DATENPFAD.v
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// Version: 1.1 bug fix
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// Version: 2.0
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// History: 1.0 first release of 30 Mai 2015
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// History: 1.1 bug fix of 7 October 2015
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// Date: 7 October 2015
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// 1.0 first release of 30 Mai 2015
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// Date: 14 August 2016
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//
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//
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// Copyright (C) 2015 Udo Moeller
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// Copyright (C) 2016 Udo Moeller
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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| Line 105... |
Line 106... |
output [40:2] DBG_IN;
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output [40:2] DBG_IN;
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output COP_GO;
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output COP_GO;
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output [127:0] COP_OUT;
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output [127:0] COP_OUT;
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reg [31:0] high_dq;
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reg [31:0] high_dq;
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reg [31:0] OUT_I;
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reg [31:0] IMMREG,MEMREG;
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reg [31:0] BYDIN; // the bypass register
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reg [31:0] BYDIN; // the bypass register
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reg LDIMR;
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wire [2:0] BITSEL;
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wire [2:0] BITSEL;
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wire [1:0] BWD;
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wire [1:0] BWD;
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wire CLR_LSB;
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wire CLR_LSB;
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wire [31:0] ERGEBNIS; // the result bus
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wire [31:0] ERGEBNIS; // the result bus
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| Line 121... |
Line 123... |
wire SELI_A;
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wire SELI_A;
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wire SELI_B;
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wire SELI_B;
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wire [2:0] SP_CMP;
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wire [2:0] SP_CMP;
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wire [31:0] SRC1; // the bus for the Source 1 operand
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wire [31:0] SRC1; // the bus for the Source 1 operand
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wire [31:0] SRC2; // the bus for the Source 2 operand
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wire [31:0] SRC2; // the bus for the Source 2 operand
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wire [31:0] OUT_I;
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wire [4:0] TT_DP;
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wire [4:0] TT_DP;
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wire TWREN; // active if FPU Trap occurs
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wire TWREN; // active if FPU Trap occurs
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wire UP_DP;
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wire UP_DP;
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wire WRADR_0;
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wire WRADR_0;
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wire WREN_L,WREN_LX;
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wire WREN_L,WREN_LX;
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| Line 133... |
Line 136... |
wire [4:0] TT_SP;
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wire [4:0] TT_SP;
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wire [31:0] addr_i;
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wire [31:0] addr_i;
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wire [2:0] DP_CMP;
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wire [2:0] DP_CMP;
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wire [31:0] DP_OUT;
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wire [31:0] DP_OUT;
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wire [31:0] SFP_DAT;
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wire [31:0] SFP_DAT;
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wire ld_out_l;
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wire [6:0] BMCODE;
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wire [6:0] BMCODE;
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wire [31:0] OUT_A,OUT_B;
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wire [31:0] OUT_A,OUT_B;
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wire SP_MUX;
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wire SP_MUX;
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wire [31:0] I_OUT;
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wire [31:0] I_OUT;
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wire [31:0] FP_OUT;
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wire [31:0] FP_OUT;
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assign BWD = OPER[9:8];
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assign BWD = OPER[9:8];
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assign OPCODE = OPER[7:0];
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assign OPCODE = OPER[7:0];
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assign ERGEBNIS = SP_MUX ? FP_OUT : I_OUT;
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assign ERGEBNIS = SP_MUX ? FP_OUT : I_OUT;
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assign WRADR_0 = WRADR[0] & ~CLR_LSB;
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assign WRADR_0 = WRADR[0] ^ CLR_LSB;
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assign ENWR = WREN_L | WREN;
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assign ENWR = WREN_L | WREN;
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assign DOWR = ENWR & TWREN;
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assign DOWR = ENWR & TWREN;
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assign WREN_L = WREN_LX & ~TRAPS[0];
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assign WREN_L = WREN_LX & ~TRAPS[0];
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| Line 165... |
Line 167... |
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assign PC_NEW = SRC1;
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assign PC_NEW = SRC1;
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always @(posedge BCLK) if (LD_OUT[1] || WREN) ACB_ZERO <= acb_zero_i;
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always @(posedge BCLK) if (LD_OUT[1] || WREN) ACB_ZERO <= acb_zero_i;
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always @(posedge BCLK) if (LD_OUT[1] || ld_out_l) high_dq <= ERGEBNIS;
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always @(posedge BCLK) if (LD_OUT[1]) high_dq <= ERGEBNIS;
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always @(posedge BCLK) if (LD_DIN) OUT_I <= LD_IMME ? IMME_Q : DIN;
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always @(posedge BCLK)
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if (LD_DIN)
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begin
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IMMREG <= IMME_Q;
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MEMREG <= DIN;
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LDIMR <= LD_IMME;
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end
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assign OUT_I = LDIMR ? IMMREG : MEMREG; // old solution had the multiplexor before the register
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always @(posedge BCLK) if (RDAA[7]) BYDIN <= ERGEBNIS;
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always @(posedge BCLK) if (RDAA[7]) BYDIN <= ERGEBNIS;
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// Register Set 1 => SRC1
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// Register Set 1 => SRC1
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| Line 337... |
Line 347... |
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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DP_FPU DOUBLE_U(
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DP_FPU DOUBLE_U(
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.BCLK(BCLK),
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.BCLK(BCLK),
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.FL(FL),
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.FL(FL),
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.BRESET(BRESET),
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.BRESET(BRESET),
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.LD_LDQ(LD_OUT[0]),
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.LD_OUT(LD_OUT),
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.WR_REG(WR_REG),
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.WR_REG(WR_REG),
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.BWD(BWD),
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.BWD(BWD),
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.FSR(FSR[8:3]),
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.FSR(FSR[8:3]),
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.OPCODE(OPCODE),
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.OPCODE(OPCODE),
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.SRC1(SRC1),
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.SRC1(SRC1),
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| Line 349... |
Line 359... |
.START(START),
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.START(START),
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.DONE(DONE),
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.DONE(DONE),
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.UP_DP(UP_DP),
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.UP_DP(UP_DP),
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.WREN_L(WREN_LX),
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.WREN_L(WREN_LX),
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.CLR_LSB(CLR_LSB),
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.CLR_LSB(CLR_LSB),
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.LD_OUT_L(ld_out_l),
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.DVZ_TRAP(TRAPS[1]),
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.DVZ_TRAP(TRAPS[1]),
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.DP_CMP(DP_CMP),
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.DP_CMP(DP_CMP),
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.DP_OUT(DP_OUT),
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.DP_OUT(DP_OUT),
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.DP_Q(DP_Q[31:0]),
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.DP_Q(DP_Q[31:0]),
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.TT_DP(TT_DP),
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.TT_DP(TT_DP),
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| Line 381... |
Line 390... |
.SP_MUX(SP_MUX),
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.SP_MUX(SP_MUX),
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.UP_SP(UP_SP),
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.UP_SP(UP_SP),
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.FP_OUT(FP_OUT),
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.FP_OUT(FP_OUT),
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.I_OUT(SFP_DAT),
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.I_OUT(SFP_DAT),
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.SP_CMP(SP_CMP),
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.SP_CMP(SP_CMP),
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.TT_SP(TT_SP));
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.TT_SP(TT_SP),
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.START(START[1]) );
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FP_STAT_REG FPS_REG(
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FP_STAT_REG FPS_REG(
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.BCLK(BCLK),
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.BCLK(BCLK),
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.BRESET(BRESET),
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.BRESET(BRESET),
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.LFSR(LD_FSR),
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.LFSR(LD_FSR),
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.WREN(ENWR),
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.WREN(ENWR),
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.WRADR(WRADR[5:4]),
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.WRADR(WRADR[5:4]),
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.UP_DP(UP_DP),
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.UP_DP(UP_DP),
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.UP_SP(UP_SP & LD_OUT[1]),
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.UP_SP(UP_SP),
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.DIN(SRC1[16:0]),
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.DIN(SRC1[16:0]),
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.TT_DP(TT_DP),
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.TT_DP(TT_DP),
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.TT_SP(TT_SP),
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.TT_SP(TT_SP),
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.FPU_TRAP(TRAPS[0]),
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.FPU_TRAP(TRAPS[0]),
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.TWREN(TWREN),
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.TWREN(TWREN),
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