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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// This file is part of the M32632 project
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// This file is part of the M32632 project
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// http://opencores.org/project,m32632
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// http://opencores.org/project,m32632
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//
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//
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// Filename: DATENPFAD.v
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// Filename: DATENPFAD.v
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// Version: 2.0
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// Version: 3.0 Cache Interface reworked
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// History: 1.1 bug fix of 7 October 2015
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// History: 2.1 bug fix of 26 November 2016
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// 1.1 bug fix of 7 October 2015
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// 1.0 first release of 30 Mai 2015
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// 1.0 first release of 30 Mai 2015
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// Date: 14 August 2016
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// Date: 2 December 2018
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//
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//
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// Copyright (C) 2016 Udo Moeller
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// Copyright (C) 2018 Udo Moeller
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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//
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//
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// You should have received a copy of the GNU Lesser General
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, download it
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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// from http://www.opencores.org/lgpl.shtml
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//
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//
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// Modules contained in this file:
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// Modules contained in this file:
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// DATENPFAD the data path of M32632
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// DATENPFAD the data path of M32632
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module DATENPFAD( BCLK, BRESET, WREN, IO_READY, LD_DIN, LD_IMME, WR_REG, IC_USER, ACC_FELD, ACC_STAT, DIN, DISP, IC_TEX,
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module DATENPFAD( BCLK, BRESET, WREN, IO_READY, LD_DIN, LD_IMME, WR_REG, IC_USER, ACC_FELD, ACC_STAT, DIN, DISP, IC_TEX,
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IMME_Q, INFO_AU, LD_OUT, DETOIP, MMU_UPDATE, OPER, PC_ARCHI, PC_ICACHE, RDAA, RDAB, START, WMASKE,
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IMME_Q, INFO_AU, LD_OUT, DETOIP, MMU_UPDATE, OPER, PC_ARCHI, PC_ICACHE, RDAA, RDAB, START, WMASKE,
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WRADR, DONE, Y_INIT, WRITE_OUT, READ_OUT, ZTEST, RMW, QWATWO, ACC_DONE, REG_OUT, PTB_SEL, PTB_WR, ACB_ZERO,
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WRADR, DONE, Y_INIT, WRITE_OUT, READ_OUT, ZTEST, RMW, QWATWO, ACC_DONE, CTRL_QW, PTB_SEL, PTB_WR, ACB_ZERO,
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ABORT, SAVE_PC, CFG, CINV, DP_Q, IVAR, MCR, PACKET, PC_NEW, PSR, SIZE, STRING, TRAPS, VADR, RWVFLAG,
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ABORT, SAVE_PC, CFG, CINV, DP_Q, IVAR, MCR, PACKET, PC_NEW, PSR, SIZE, STRING, TRAPS, VADR, RWVFLAG,
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DBG_HIT, DBG_IN, COP_GO, COP_OP, COP_IN, COP_DONE, COP_OUT);
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DBG_HIT, DBG_IN, COP_GO, COP_OP, COP_IN, COP_DONE, COP_OUT);
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input BCLK;
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input BCLK;
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input BRESET;
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input BRESET;
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output READ_OUT;
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output READ_OUT;
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output ZTEST;
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output ZTEST;
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output RMW;
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output RMW;
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output QWATWO;
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output QWATWO;
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output ACC_DONE;
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output ACC_DONE;
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output REG_OUT;
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output [1:0] CTRL_QW;
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output PTB_SEL;
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output PTB_SEL;
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output PTB_WR;
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output PTB_WR;
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output reg ACB_ZERO;
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output reg ACB_ZERO;
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output ABORT;
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output ABORT;
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output SAVE_PC;
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output SAVE_PC;
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wire [1:0] BWD;
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wire [1:0] BWD;
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wire CLR_LSB;
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wire CLR_LSB;
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wire [31:0] ERGEBNIS; // the result bus
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wire [31:0] ERGEBNIS; // the result bus
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wire FL;
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wire FL;
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wire [31:0] FSR;
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wire [31:0] FSR;
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wire [63:0] MRESULT;
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wire [32:0] MRESULT;
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wire [7:0] OPCODE;
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wire [7:0] OPCODE;
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wire SELI_A;
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wire SELI_A;
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wire SELI_B;
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wire SELI_B;
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wire [2:0] SP_CMP;
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wire [2:0] SP_CMP;
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wire [31:0] SRC1; // the bus for the Source 1 operand
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wire [31:0] SRC1; // the bus for the Source 1 operand
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.SELI(SELI_B),
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.SELI(SELI_B),
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.DOUT(OUT_B));
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.DOUT(OUT_B));
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assign SRC2 = SELI_B ? OUT_I : OUT_B;
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assign SRC2 = SELI_B ? OUT_I : OUT_B;
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MULFILTER M_FILTER(
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MULFILTER M_FILTER( // signed multiplier 32 * 32 bits = 64 bits
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.FLOAT(OPCODE[2]),
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.BWD(BWD),
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.BWD(BWD),
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.SRC1(SRC1),
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.SRC1(SRC1),
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.SRC2(SRC2),
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.SRC2(SRC2),
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.DEST1(DEST1),
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.MRESULT(MRESULT));
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.DEST2(DEST2));
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SIGNMUL S_MULTI( // signed multiplier 32 * 32 bits = 64 bits
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.dataa(DEST1),
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.datab(DEST2),
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.result(MRESULT));
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BITMASK BITM_U(
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BITMASK BITM_U(
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.AA(BMCODE),
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.AA(BMCODE),
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.DOUT(BMASKE));
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.DOUT(BMASKE));
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.PC_ARCHI(PC_ARCHI),
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.PC_ARCHI(PC_ARCHI),
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.PC_ICACHE(PC_ICACHE),
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.PC_ICACHE(PC_ICACHE),
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.SRC1(SRC1),
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.SRC1(SRC1),
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.SRC2(SRC2),
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.SRC2(SRC2),
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.SRC2SEL(ACC_FELD[1:0]),
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.SRC2SEL(ACC_FELD[1:0]),
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.REG_OUT(REG_OUT),
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.CTRL_QW(CTRL_QW),
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.ACC_DONE(ACC_DONE),
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.ACC_DONE(ACC_DONE),
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.READ_OUT(READ_OUT),
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.READ_OUT(READ_OUT),
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.WRITE_OUT(WRITE_OUT),
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.WRITE_OUT(WRITE_OUT),
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.ABORT(ABORT),
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.ABORT(ABORT),
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.ADDR(addr_i),
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.ADDR(addr_i),
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SP_FPU SINGLE_U(
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SP_FPU SINGLE_U(
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.FL(FL),
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.FL(FL),
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.BCLK(BCLK),
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.BCLK(BCLK),
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.BWD(BWD),
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.BWD(BWD),
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.FSR(FSR[8:3]),
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.FSR(FSR[8:3]),
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.MRESULT(MRESULT[47:0]),
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.OPCODE(OPCODE),
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.OPCODE(OPCODE),
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.SRC1(SRC1),
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.SRC1(SRC1),
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.SRC2(SRC2),
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.SRC2(SRC2),
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.LD_FSR(LD_FSR),
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.LD_FSR(LD_FSR),
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.SP_MUX(SP_MUX),
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.SP_MUX(SP_MUX),
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.UP_SP(UP_SP),
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.UP_SP(UP_SP),
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.FP_OUT(FP_OUT),
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.FP_OUT(FP_OUT),
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.I_OUT(SFP_DAT),
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.I_OUT(SFP_DAT),
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.SP_CMP(SP_CMP),
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.SP_CMP(SP_CMP),
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.TT_SP(TT_SP),
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.TT_SP(TT_SP),
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.START(START[1]) );
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.START(START[1]) ); // Aenderung
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FP_STAT_REG FPS_REG(
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FP_STAT_REG FPS_REG(
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.BCLK(BCLK),
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.BCLK(BCLK),
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.BRESET(BRESET),
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.BRESET(BRESET),
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.LFSR(LD_FSR),
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.LFSR(LD_FSR),
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.WREN(ENWR),
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.WREN(ENWR),
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.WRADR(WRADR[5:4]),
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.WRADR(WRADR[5:4]),
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.UP_DP(UP_DP),
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.UP_DP(UP_DP),
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.UP_SP(UP_SP),
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.UP_SP(UP_SP), // & LD_OUT[1]), Aenderung
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.DIN(SRC1[16:0]),
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.DIN(SRC1[16:0]),
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.TT_DP(TT_DP),
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.TT_DP(TT_DP),
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.TT_SP(TT_SP),
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.TT_SP(TT_SP),
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.FPU_TRAP(TRAPS[0]),
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.FPU_TRAP(TRAPS[0]),
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.TWREN(TWREN),
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.TWREN(TWREN),
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