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//
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//
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// This file is part of the M32632 project
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// This file is part of the M32632 project
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// http://opencores.org/project,m32632
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// http://opencores.org/project,m32632
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//
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//
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// Filename: DATENPFAD.v
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// Filename: DATENPFAD.v
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// Version: 3.0 Cache Interface reworked
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// Project: M32632
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// History: 2.1 bug fix of 26 November 2016
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// Version: 3.1 bug fix of 25 February 2019
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// History: 3.0 Cache Interface reworked
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// 2.1 bug fix of 26 November 2016
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// 1.1 bug fix of 7 October 2015
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// 1.1 bug fix of 7 October 2015
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// 1.0 first release of 30 Mai 2015
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// 1.0 first release of 30 Mai 2015
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// Date: 2 December 2018
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// Author: Udo Moeller
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// Date: 8 July 2017
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//
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//
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// Copyright (C) 2018 Udo Moeller
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// Copyright (C) 2019 Udo Moeller
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module DATENPFAD( BCLK, BRESET, WREN, IO_READY, LD_DIN, LD_IMME, WR_REG, IC_USER, ACC_FELD, ACC_STAT, DIN, DISP, IC_TEX,
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module DATENPFAD( BCLK, BRESET, WREN, IO_READY, LD_DIN, LD_IMME, WR_REG, IC_USER, ACC_FELD, ACC_STAT, DIN, DISP, IC_TEX,
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IMME_Q, INFO_AU, LD_OUT, DETOIP, MMU_UPDATE, OPER, PC_ARCHI, PC_ICACHE, RDAA, RDAB, START, WMASKE,
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IMME_Q, INFO_AU, LD_OUT, DETOIP, MMU_UPDATE, OPER, PC_ARCHI, PC_ICACHE, RDAA, RDAB, START, WMASKE,
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WRADR, DONE, Y_INIT, WRITE_OUT, READ_OUT, ZTEST, RMW, QWATWO, ACC_DONE, CTRL_QW, PTB_SEL, PTB_WR, ACB_ZERO,
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WRADR, DONE, Y_INIT, WRITE_OUT, READ_OUT, ZTEST, RMW, QWATWO, ACC_DONE, CTRL_QW, PTB_SEL, PTB_WR, ACB_ZERO,
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ABORT, SAVE_PC, CFG, CINV, DP_Q, IVAR, MCR, PACKET, PC_NEW, PSR, SIZE, STRING, TRAPS, VADR, RWVFLAG,
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ABORT, SAVE_PC, CFG, CINV, DP_Q, IVAR, IVAR_MUX, MCR, PACKET, PC_NEW, PSR, SIZE, STRING, TRAPS, VADR, RWVFLAG,
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DBG_HIT, DBG_IN, COP_GO, COP_OP, COP_IN, COP_DONE, COP_OUT);
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DBG_HIT, DBG_IN, COP_GO, COP_OP, COP_IN, COP_DONE, COP_OUT);
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input BCLK;
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input BCLK;
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input BRESET;
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input BRESET;
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input WREN; // write enable of the register file
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input WREN; // write enable of the register file
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output SAVE_PC;
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output SAVE_PC;
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output [12:0] CFG;
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output [12:0] CFG;
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output [3:0] CINV;
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output [3:0] CINV;
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output [63:0] DP_Q;
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output [63:0] DP_Q;
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output [1:0] IVAR;
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output [1:0] IVAR;
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output IVAR_MUX;
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output [3:0] MCR;
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output [3:0] MCR;
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output [3:0] PACKET;
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output [3:0] PACKET;
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output [31:0] PC_NEW;
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output [31:0] PC_NEW;
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output [11:0] PSR;
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output [11:0] PSR;
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output [1:0] SIZE;
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output [1:0] SIZE;
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wire [31:0] OUT_A,OUT_B;
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wire [31:0] OUT_A,OUT_B;
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wire SP_MUX;
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wire SP_MUX;
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wire [31:0] I_OUT;
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wire [31:0] I_OUT;
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wire [31:0] FP_OUT;
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wire [31:0] FP_OUT;
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wire DOWR;
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wire DOWR;
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wire [31:0] DEST1,DEST2;
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wire ENWR;
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wire ENWR;
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wire [3:0] OVF_BCD;
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wire [3:0] OVF_BCD;
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wire [3:0] DSR;
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wire [3:0] DSR;
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wire acb_zero_i;
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wire acb_zero_i;
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wire [31:0] BMASKE;
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wire [31:0] BMASKE;
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.PTB_WR(PTB_WR),
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.PTB_WR(PTB_WR),
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.PTB_SEL(PTB_SEL),
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.PTB_SEL(PTB_SEL),
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.CFG(CFG),
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.CFG(CFG),
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.CINV(CINV),
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.CINV(CINV),
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.IVAR(IVAR),
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.IVAR(IVAR),
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.IVAR_MUX(IVAR_MUX),
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.Y_INIT(Y_INIT),
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.Y_INIT(Y_INIT),
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.MCR(MCR),
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.MCR(MCR),
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.DBG_TRAPS(TRAPS[5:3]),
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.DBG_TRAPS(TRAPS[5:3]),
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.PC_ARCHI(PC_ARCHI),
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.PC_ARCHI(PC_ARCHI),
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.DSR(DSR),
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.DSR(DSR),
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