| Line 2... |
Line 2... |
//
|
//
|
// This file is part of the M32632 project
|
// This file is part of the M32632 project
|
// http://opencores.org/project,m32632
|
// http://opencores.org/project,m32632
|
//
|
//
|
// Filename: DCACHE.v
|
// Filename: DCACHE.v
|
// Version: 3.0 Cache Interface reworked
|
// Version: 3.2 bug fix
|
// History: 2.1 bug fix of November 2016
|
// History: 3.0 Cache Interface reworked
|
|
// 2.1 bug fix of November 2016
|
// 2.0 50 MHz release of 14 August 2016
|
// 2.0 50 MHz release of 14 August 2016
|
// 1.1 bug fix of 7 October 2015
|
// 1.1 bug fix of 7 October 2015
|
// 1.0 first release of 30 Mai 2015
|
// 1.0 first release of 30 Mai 2015
|
// Date: 2 December 2018
|
// Date: 17 January 2021
|
//
|
//
|
// Copyright (C) 2018 Udo Moeller
|
// Copyright (C) 2021 Udo Moeller
|
//
|
//
|
// This source file may be used and distributed without
|
// This source file may be used and distributed without
|
// restriction provided that this copyright statement is not
|
// restriction provided that this copyright statement is not
|
// removed from the file and that any derivative work contains
|
// removed from the file and that any derivative work contains
|
// the original copyright notice and the associated disclaimer.
|
// the original copyright notice and the associated disclaimer.
|
| Line 169... |
Line 170... |
wire PD_MUX;
|
wire PD_MUX;
|
wire [19:0] PTE_DAT;
|
wire [19:0] PTE_DAT;
|
wire PKEEP;
|
wire PKEEP;
|
wire XADDR2;
|
wire XADDR2;
|
wire [28:12] TAGDAT;
|
wire [28:12] TAGDAT;
|
|
wire clr_up;
|
|
|
// +++++++++++++++++++ Memories ++++++++++++++++++++
|
// +++++++++++++++++++ Memories ++++++++++++++++++++
|
|
|
reg [7:0] DATA0_P [0:255]; // Data Set 0 : 4 kBytes
|
reg [7:0] DATA0_P [0:255]; // Data Set 0 : 4 kBytes
|
reg [7:0] DATA0_O [0:255];
|
reg [7:0] DATA0_O [0:255];
|
| Line 275... |
Line 277... |
begin
|
begin
|
DRAM_DI <= {(PD_MUX ? PTE_DAT[19:16] : ENBYTE),WRDATA[31:16],
|
DRAM_DI <= {(PD_MUX ? PTE_DAT[19:16] : ENBYTE),WRDATA[31:16],
|
(PD_MUX ? PTE_DAT[15:0] : WRDATA[15:0])};
|
(PD_MUX ? PTE_DAT[15:0] : WRDATA[15:0])};
|
AUX_ALT <= DFF_QWEXT | IO_RD;
|
AUX_ALT <= DFF_QWEXT | IO_RD;
|
DFF_QWEXT <= IO_RD & SIZE[0] & SIZE[1];
|
DFF_QWEXT <= IO_RD & SIZE[0] & SIZE[1];
|
VADR_R <= VADR;
|
VADR_R[23:0] <= VADR[23:0];
|
end
|
end
|
|
|
|
assign clr_up = ~(DRAMSZ == 3'd0);
|
|
always @(posedge BCLK or negedge clr_up)
|
|
if (!clr_up) VADR_R[31:24] <= 8'd0;
|
|
else VADR_R[31:24] <= VADR[31:24];
|
|
|
always @(posedge BCLK) if (MDONE) CAPDAT <= CAP_Q;
|
always @(posedge BCLK) if (MDONE) CAPDAT <= CAP_Q;
|
|
|
// +++++++++++++++++++++++++ Cache Valid +++++++++++++++++++
|
// +++++++++++++++++++++++++ Cache Valid +++++++++++++++++++
|
|
|
NEU_VALID VALID_RAM(
|
NEU_VALID VALID_RAM(
|
