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[/] [m32632/] [trunk/] [rtl/] [DCACHE.v] - Diff between revs 11 and 12

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//
//
// This file is part of the M32632 project
// This file is part of the M32632 project
// http://opencores.org/project,m32632
// http://opencores.org/project,m32632
//
//
// Filename: DCACHE.v
// Filename: DCACHE.v
// Version:  1.0
// Version:  1.1 bug fix
// Date:     30 May 2015
// History:  1.0 first release of 30 Mai 2015
 
// Date:     7 October 2015
//
//
// Copyright (C) 2015 Udo Moeller
// Copyright (C) 2015 Udo Moeller
// 
// 
// This source file may be used and distributed without 
// This source file may be used and distributed without 
// restriction provided that this copyright statement is not 
// restriction provided that this copyright statement is not 
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//      Modules contained in this file:
//      Modules contained in this file:
//      DCACHE          the data cache of M32632
//      DCACHE          the data cache of M32632
//
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 
 
module DCACHE(  BCLK, MCLK,     WRCFG, MDONE, BRESET, PTB_WR, PTB_SEL, IO_READY, REG_OUT, PSR_USER, WRITE, READ, RMW,
module DCACHE(  BCLK, MCLK,     WRCFG, MDONE, BRESET, PTB_WR, PTB_SEL, IO_READY, REG_OUT, PSR_USER, WRITE, READ, RMW, QWATWO,
                                WAMUX, ENWR, IC_PREQ, FILLRAM, CFG, CINVAL, DMA_AA, DP_Q, DRAM_Q, IC_VA, ICTODC, IO_Q, IVAR, MCR_FLAGS,
                                WAMUX, ENWR, IC_PREQ, FILLRAM, CFG, CINVAL, DMA_AA, DP_Q, DRAM_Q, IC_VA, ICTODC, IO_Q, IVAR, MCR_FLAGS,
                                PACKET, SIZE, VADR,     WADDR, WCTRL, IO_RD, IO_WR, DRAM_ACC, DRAM_WR, INIT_RUN, PTE_STAT, KDET, HLDA,
                                PACKET, SIZE, VADR,     WADDR, WCTRL, IO_RD, IO_WR, DRAM_ACC, DRAM_WR, INIT_RUN, PTE_STAT, KDET, HLDA,
                                ACC_STAT, DP_DI, DRAM_A, DRAM_DI, IACC_STAT, IC_SIGS, IO_A, IO_BE, IO_DI, KOLLI_A, MMU_DIN, ZTEST,
                                ACC_STAT, DP_DI, DRAM_A, DRAM_DI, IACC_STAT, IC_SIGS, IO_A, IO_BE, IO_DI, KOLLI_A, MMU_DIN, ZTEST,
                                RWVAL, RWVFLAG, DBG_IN, DBG_HIT, ENDRAM );
                                RWVAL, RWVFLAG, DBG_IN, DBG_HIT, ENDRAM );
 
 
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input                   PSR_USER;
input                   PSR_USER;
input                   WRITE;
input                   WRITE;
input                   READ;
input                   READ;
input                   ZTEST;
input                   ZTEST;
input                   RMW;
input                   RMW;
 
input                   QWATWO;
input                   WAMUX;
input                   WAMUX;
input                   ENWR;
input                   ENWR;
input                   IC_PREQ;
input                   IC_PREQ;
input                   FILLRAM;
input                   FILLRAM;
input    [1:0]   CFG;
input    [1:0]   CFG;
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assign  DAT_SET = WRITE ? WRDATA : DRAM_Q ;
assign  DAT_SET = WRITE ? WRDATA : DRAM_Q ;
 
 
assign  BE_SET  = ENBYTE | {~WRITE,~WRITE,~WRITE,~WRITE};
assign  BE_SET  = ENBYTE | {~WRITE,~WRITE,~WRITE,~WRITE};
 
 
assign  ADDR    = KOMUX ? KOLLI_A : {RADR[27:12],VADR_R[11:4]} ;
assign  ADDR    = KDET ? KOLLI_A : {RADR[27:12],VADR_R[11:4]} ;
 
 
assign  A_SET   = WAMUX ? WADDR : VADR_R[11:2] ;
assign  A_SET   = WAMUX ? WADDR : VADR_R[11:2] ;
 
 
assign  TAGA    = KOMUX ? KOLLI_A[11:4] : VADR[11:4] ;
assign  TAGA    = KOMUX ? KOLLI_A[11:4] : VADR[11:4] ;
 
 
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        .CA_HIT(CA_HIT),
        .CA_HIT(CA_HIT),
        .READ(READ),
        .READ(READ),
        .WRITE(WRITE),
        .WRITE(WRITE),
        .ZTEST(ZTEST),
        .ZTEST(ZTEST),
        .RMW(RMW),
        .RMW(RMW),
 
        .QWATWO(QWATWO),
        .USE_CA(USE_CA),
        .USE_CA(USE_CA),
        .PTB_WR(PTB_WR),
        .PTB_WR(PTB_WR),
        .PTB_SEL(PTB_SEL),
        .PTB_SEL(PTB_SEL),
        .SEL_PTB1(SEL_PTB1),
        .SEL_PTB1(SEL_PTB1),
        .IO_READY(IO_READY),
        .IO_READY(IO_READY),

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